CLK_TOP_MSDC50_0_HCLK_SEL (reference) in projects: kernel - OpenGrok search results

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Searched refs:CLK_TOP_MSDC50_0_HCLK_SEL (Results 1 - 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A D	mt6765-clk.h	`143 #define CLK_TOP_MSDC50_0_HCLK_SEL 108 macro`
H A D	mt2712-clk.h	`142 #define CLK_TOP_MSDC50_0_HCLK_SEL 111 macro`
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A D	mt6765-clk.h	`143 #define CLK_TOP_MSDC50_0_HCLK_SEL 108 macro`
H A D	mt2712-clk.h	`142 #define CLK_TOP_MSDC50_0_HCLK_SEL 111 macro`
/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A D	mt6765-clk.h	`143 #define CLK_TOP_MSDC50_0_HCLK_SEL 108 macro`
H A D	mt2712-clk.h	`142 #define CLK_TOP_MSDC50_0_HCLK_SEL 111 macro`
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A D	mt6765-clk.h	`143 #define CLK_TOP_MSDC50_0_HCLK_SEL 108 macro`
H A D	mt2712-clk.h	`142 #define CLK_TOP_MSDC50_0_HCLK_SEL 111 macro`
/kernel/linux/linux-6.6/drivers/clk/mediatek/
H A D	clk-mt2712.c	`661 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,`
H A D	clk-mt6765.c	`409 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",`
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A D	clk-mt2712.c	`765 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",`
H A D	clk-mt6765.c	`406 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",`

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