| /kernel/linux/linux-6.6/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 93 #define CLK_TOP_MM_SEL 82 macro
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| H A D | mediatek,mt8365-clk.h | 73 #define CLK_TOP_MM_SEL 63 macro
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| H A D | mt8173-clk.h | 95 #define CLK_TOP_MM_SEL 85 macro
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| H A D | mt6765-clk.h | 133 #define CLK_TOP_MM_SEL 98 macro
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| H A D | mt2701-clk.h | 87 #define CLK_TOP_MM_SEL 76 macro
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| H A D | mt2712-clk.h | 132 #define CLK_TOP_MM_SEL 101 macro
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| /kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 93 #define CLK_TOP_MM_SEL 82 macro
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| H A D | mediatek,mt8365-clk.h | 73 #define CLK_TOP_MM_SEL 63 macro
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| H A D | mt6765-clk.h | 133 #define CLK_TOP_MM_SEL 98 macro
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| H A D | mt8173-clk.h | 95 #define CLK_TOP_MM_SEL 85 macro
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| H A D | mt2701-clk.h | 87 #define CLK_TOP_MM_SEL 76 macro
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| H A D | mt2712-clk.h | 132 #define CLK_TOP_MM_SEL 101 macro
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| /kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt6765-clk.h | 133 #define CLK_TOP_MM_SEL 98 macro
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| H A D | mt8173-clk.h | 95 #define CLK_TOP_MM_SEL 85 macro
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| H A D | mt2701-clk.h | 87 #define CLK_TOP_MM_SEL 76 macro
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| H A D | mt2712-clk.h | 132 #define CLK_TOP_MM_SEL 101 macro
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| H A D | mt6765-clk.h | 133 #define CLK_TOP_MM_SEL 98 macro
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| H A D | mt8173-clk.h | 95 #define CLK_TOP_MM_SEL 85 macro
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| H A D | mt2701-clk.h | 87 #define CLK_TOP_MM_SEL 76 macro
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| H A D | mt2712-clk.h | 132 #define CLK_TOP_MM_SEL 101 macro
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| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 458 TOP_MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x40, 24, 3, 31, 0),
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| H A D | clk-mt8173-topckgen.c | 537 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
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| H A D | clk-mt2712.c | 648 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31),
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| H A D | clk-mt6765.c | 376 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
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| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| H A D | clk-mt2701.c | 494 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
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