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Searched refs:CLK_TOP_DDRPHYCFG_SEL (Results 1 - 25 of 39) sorted by relevance

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/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt7622-clk.h70 #define CLK_TOP_DDRPHYCFG_SEL 58 macro
H A Dmt8516-clk.h171 #define CLK_TOP_DDRPHYCFG_SEL 139 macro
H A Dmt7629-clk.h85 #define CLK_TOP_DDRPHYCFG_SEL 75 macro
H A Dmt8135-clk.h94 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
H A Dmt8173-clk.h94 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A Dmt7622-clk.h70 #define CLK_TOP_DDRPHYCFG_SEL 58 macro
H A Dmt7629-clk.h85 #define CLK_TOP_DDRPHYCFG_SEL 75 macro
H A Dmt8135-clk.h94 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
H A Dmt8516-clk.h171 #define CLK_TOP_DDRPHYCFG_SEL 139 macro
H A Dmt8173-clk.h94 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h92 #define CLK_TOP_DDRPHYCFG_SEL 81 macro
H A Dmt8516-clk.h171 #define CLK_TOP_DDRPHYCFG_SEL 139 macro
H A Dmt7622-clk.h70 #define CLK_TOP_DDRPHYCFG_SEL 58 macro
H A Dmt7629-clk.h85 #define CLK_TOP_DDRPHYCFG_SEL 75 macro
H A Dmt8135-clk.h94 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
H A Dmt8173-clk.h94 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt8516-clk.h171 #define CLK_TOP_DDRPHYCFG_SEL 139 macro
H A Dmediatek,mt6795-clk.h92 #define CLK_TOP_DDRPHYCFG_SEL 81 macro
H A Dmt7622-clk.h70 #define CLK_TOP_DDRPHYCFG_SEL 58 macro
H A Dmt7629-clk.h85 #define CLK_TOP_DDRPHYCFG_SEL 75 macro
H A Dmt8135-clk.h94 #define CLK_TOP_DDRPHYCFG_SEL 83 macro
H A Dmt8173-clk.h94 #define CLK_TOP_DDRPHYCFG_SEL 84 macro
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A Dclk-mt7622.c519 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
641 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_topckgen_init()
H A Dclk-mt7629.c491 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
597 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_topckgen_init()
/kernel/linux/linux-6.6/drivers/clk/mediatek/
H A Dclk-mt7629.c466 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
573 clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk); in mtk_topckgen_init()

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