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Searched refs:CLK_TOP_APLL_DIV_PDN1 (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt2712-clk.h210 #define CLK_TOP_APLL_DIV_PDN1 179 macro
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A Dmt2712-clk.h210 #define CLK_TOP_APLL_DIV_PDN1 179 macro
/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A Dmt2712-clk.h210 #define CLK_TOP_APLL_DIV_PDN1 179 macro
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt2712-clk.h210 #define CLK_TOP_APLL_DIV_PDN1 179 macro
/kernel/linux/linux-6.6/drivers/clk/mediatek/
H A Dclk-mt2712.c824 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A Dclk-mt2712.c981 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),

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