Searched refs:CLK_TOP_APLL2_DIV0 (Results 1 - 9 of 9) sorted by relevance
| /kernel/linux/linux-6.6/include/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 132 #define CLK_TOP_APLL2_DIV0 121 macro
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| H A D | mt8173-clk.h | 137 #define CLK_TOP_APLL2_DIV0 127 macro
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| /kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mediatek,mt6795-clk.h | 132 #define CLK_TOP_APLL2_DIV0 121 macro
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| H A D | mt8173-clk.h | 137 #define CLK_TOP_APLL2_DIV0 127 macro
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| /kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8173-clk.h | 137 #define CLK_TOP_APLL2_DIV0 127 macro
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| H A D | mt8173-clk.h | 137 #define CLK_TOP_APLL2_DIV0 127 macro
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| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 518 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
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| H A D | clk-mt8173-topckgen.c | 613 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
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| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| H A D | clk-mt8173.c | 602 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
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