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Searched refs:CLKID_VCLK_DIV4 (Results 1 - 20 of 20) sorted by relevance

/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dgxbb-clkc.h136 #define CLKID_VCLK_DIV4 187 macro
H A Dg12a-clkc.h115 #define CLKID_VCLK_DIV4 150 macro
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A Dgxbb-clkc.h136 #define CLKID_VCLK_DIV4 187 macro
H A Dg12a-clkc.h115 #define CLKID_VCLK_DIV4 150 macro
/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A Daxg-clkc.h134 #define CLKID_VCLK_DIV4 124 macro
H A Dgxbb-clkc.h195 #define CLKID_VCLK_DIV4 187 macro
H A Dmeson8b-clkc.h151 #define CLKID_VCLK_DIV4 144 macro
H A Dg12a-clkc.h161 #define CLKID_VCLK_DIV4 150 macro
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Daxg-clkc.h134 #define CLKID_VCLK_DIV4 124 macro
H A Dmeson8b-clkc.h151 #define CLKID_VCLK_DIV4 144 macro
H A Dgxbb-clkc.h195 #define CLKID_VCLK_DIV4 187 macro
H A Dg12a-clkc.h161 #define CLKID_VCLK_DIV4 150 macro
/kernel/linux/linux-5.10/drivers/clk/meson/
H A Dmeson8b.h123 #define CLKID_VCLK_DIV4 144 macro
H A Dmeson8b.c2860 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3067 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3285 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
H A Dgxbb.c2912 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
3123 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
H A Dg12a.c4337 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4563 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4818 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
/kernel/linux/linux-6.6/drivers/clk/meson/
H A Dmeson8b.c2921 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3125 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
3340 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
H A Dgxbb.c2914 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
3121 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
H A Dg12a.c4401 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4626 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4886 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
H A Daxg.c2019 [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,

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