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Searched refs:CHL_INT0_MSK (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/scsi/hisi_sas/
H A Dhisi_sas_v1_hw.c178 #define CHL_INT0_MSK (PORT_BASE + 0x1bc) macro
1400 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee); in int_phyup_v1_hw()
1445 irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK); in int_abnormal_v1_hw()
1446 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff); in int_abnormal_v1_hw()
1481 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, in int_abnormal_v1_hw()
1484 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, in int_abnormal_v1_hw()
1719 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee); in interrupt_openall_v1_hw()
1724 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, in interrupt_openall_v1_hw()
H A Dhisi_sas_v3_hw.c280 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) macro
2820 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
H A Dhisi_sas_v2_hw.c245 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) macro
/kernel/linux/linux-6.6/drivers/scsi/hisi_sas/
H A Dhisi_sas_v1_hw.c178 #define CHL_INT0_MSK (PORT_BASE + 0x1bc) macro
1389 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee); in int_phyup_v1_hw()
1433 irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK); in int_abnormal_v1_hw()
1434 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff); in int_abnormal_v1_hw()
1470 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, in int_abnormal_v1_hw()
1473 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, in int_abnormal_v1_hw()
1699 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee); in interrupt_openall_v1_hw()
1704 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, in interrupt_openall_v1_hw()
H A Dhisi_sas_v3_hw.c282 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) macro
2974 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
H A Dhisi_sas_v2_hw.c245 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) macro

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