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Searched refs:CE4100_SSCR1_RFT (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/include/linux/
H A Dpxa2xx_ssp.h105 #define CE4100_SSCR1_RFT GENMASK(11, 10) /* Receive FIFO Threshold (mask) */ macro
/kernel/linux/linux-6.6/include/linux/
H A Dpxa2xx_ssp.h104 #define CE4100_SSCR1_RFT GENMASK(11, 10) /* Receive FIFO Threshold (mask) */ macro
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-pxa2xx.c64 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
266 mask = CE4100_SSCR1_RFT; in pxa2xx_spi_clear_rx_thre()
598 mask |= CE4100_SSCR1_RFT; in reset_sccr1()
1296 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | in setup()
/kernel/linux/linux-5.10/drivers/spi/
H A Dspi-pxa2xx.c64 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
255 mask = CE4100_SSCR1_RFT; in pxa2xx_spi_clear_rx_thre()
611 sccr1_reg &= ~CE4100_SSCR1_RFT; in reset_sccr1()
1384 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | in setup()

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