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Searched refs:CCCR (Results 1 - 9 of 9) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/pxa/
H A Dclk-pxa25x.c43 * Various clock factors driven by the CCCR register.
89 * Get the clock frequency as reflected by CCCR and the turbo flag.
124 unsigned long cccr = readl(CCCR); in clk_pxa25x_memory_get_rate()
187 /* CPU MEMBUS CCCR DIV2 CCLKCFG */
228 unsigned long cccr = readl(CCCR); in clk_pxa25x_run_get_rate()
239 unsigned long clkcfg, cccr = readl(CCCR); in clk_pxa25x_cpll_get_rate()
271 pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, MDREFR, CCCR); in clk_pxa25x_cpll_set_rate()
H A Dclk-pxa27x.c191 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
199 * In CCCR:
263 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, MDREFR, CCCR); in clk_pxa27x_cpll_set_rate()
275 unsigned long cccr = readl(CCCR); in clk_pxa27x_lcd_base_get_rate()
418 unsigned long cccr = readl(CCCR); in clk_pxa27x_memory_get_rate()
437 unsigned long cccr = readl(CCCR); in clk_pxa27x_memory_get_parent()
/kernel/linux/linux-6.6/drivers/clk/pxa/
H A Dclk-pxa25x.c42 * Various clock factors driven by the CCCR register.
68 * Get the clock frequency as reflected by CCCR and the turbo flag.
103 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa25x_memory_get_rate()
166 /* CPU MEMBUS CCCR DIV2 CCLKCFG */
207 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa25x_run_get_rate()
218 unsigned long clkcfg, cccr = readl(clk_regs + CCCR); in clk_pxa25x_cpll_get_rate()
250 pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, clk_regs + CCCR); in clk_pxa25x_cpll_set_rate()
H A Dclk-pxa27x.c169 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
177 * In CCCR:
241 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, clk_regs + CCCR); in clk_pxa27x_cpll_set_rate()
253 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa27x_lcd_base_get_rate()
396 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa27x_memory_get_rate()
415 unsigned long cccr = readl(clk_regs + CCCR); in clk_pxa27x_memory_get_parent()
H A Dclk-pxa2xx.h5 #define CCCR (0x0000) /* Core Clock Configuration Register */ macro
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
H A Dsleep.S69 ldr r6, =CCCR
72 ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
112 ldr r6, =CCCR
/kernel/linux/linux-6.6/arch/arm/mach-pxa/
H A Dsleep.S70 ldr r6, =CCCR
73 ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
113 ldr r6, =CCCR
H A Dpxa2xx-regs.h134 #define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */ macro
/kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/
H A Dpxa2xx-regs.h134 #define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */ macro

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