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Searched refs:BLT_RING_BASE (Results 1 - 14 of 14) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c647 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
680 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
687 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
688 REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
689 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),
690 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),
691 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),
692 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),
693 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),
694 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE,
[all...]
H A Dintel_gvt_mmio_table.c37 MMIO_F(prefix(BLT_RING_BASE), s); \
600 MMIO_D(ECOSKPD(BLT_RING_BASE)); in iterate_generic_mmio()
1243 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40); in iterate_bxt_mmio()
H A Di915_reg.h918 #define BLT_RING_BASE 0x22000 macro
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c69 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
70 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
71 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
72 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
73 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
121 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
122 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
123 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
124 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
125 {BCS0, RING_EXCC(BLT_RING_BASE),
[all...]
H A Dhandlers.c1912 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
3367 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c73 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
74 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
75 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
76 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
77 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
127 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
128 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
129 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
130 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
131 {BCS0, RING_EXCC(BLT_RING_BASE),
[all...]
H A Dhandlers.c2160 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
2785 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
H A Dintel_engine_regs.h41 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
42 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
43 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
H A Dintel_rc6.c475 (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 && in bxt_check_bios_rc6_setup()
H A Dintel_engine_cs.c75 { .graphics_ver = 6, .base = BLT_RING_BASE }
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c634 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
667 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
674 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),
675 REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),
H A Dintel_uncore.c952 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
960 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
974 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */
H A Di915_reg.h2507 #define BLT_RING_BASE 0x22000 macro
2522 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2523 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2524 #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dintel_engine_cs.c86 { .gen = 6, .base = BLT_RING_BASE }

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