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Help
Searched
refs:BIT9
(Results
1 - 25
of
43
) sorted by relevance
1
2
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
H
A
D
rtl8723b_spec.h
217
#define IMR_CPWM2_8723B
BIT9
/* CPU power Mode exchange INT Status, Write 1 clear */
246
#define IMR_TXFOVW_8723B
BIT9
/* Transmit FIFO Overflow */
H
A
D
hal_com_reg.h
617
#define RRSR_36M
BIT9
795
#define IMR_BDOK
BIT9
/* Beacon Queue DMA OK Interrup */
811
#define IMR_C2HCMD
BIT9
843
#define PHIMR_CPWM2
BIT9
866
#define PHIMR_TXFOVW
BIT9
894
#define UHIMR_CPWM2
BIT9
919
#define UHIMR_TXFOVW
BIT9
948
#define IMR_CPWM2_88E
BIT9
/* CPU power Mode exchange INT Status, Write 1 clear */
977
#define IMR_TXFOVW_88E
BIT9
/* Transmit FIFO Overflow */
1042
#define RCR_AICV
BIT9
/* Accep
[all...]
H
A
D
osdep_service.h
30
#define
BIT9
0x00000200
macro
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/include/
H
A
D
rtl8723b_spec.h
205
#define IMR_CPWM2_8723B
BIT9
/* CPU power Mode exchange INT Status, Write 1 clear */
234
#define IMR_TXFOVW_8723B
BIT9
/* Transmit FIFO Overflow */
H
A
D
osdep_service.h
26
#define
BIT9
0x00000200
macro
H
A
D
hal_com_reg.h
556
#define RRSR_36M
BIT9
706
#define IMR_BDOK
BIT9
/* Beacon Queue DMA OK Interrupt */
722
#define IMR_C2HCMD
BIT9
753
#define RCR_AICV
BIT9
/* Accept ICV error packet */
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H
A
D
halbt_precomp.h
40
#define
BIT9
0x00000200
macro
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H
A
D
halbt_precomp.h
40
#define
BIT9
0x00000200
macro
/kernel/linux/linux-6.6/drivers/staging/rtl8192e/rtl8192e/
H
A
D
r8192E_hw.h
113
#define IMR_BDOK
BIT9
190
#define RRSR_36M
BIT9
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
H
A
D
r8192E_hw.h
219
#define IMR_BDOK
BIT9
240
#define TPPoll_StopBK
BIT9
370
#define RRSR_36M
BIT9
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
H
A
D
Hal8723BReg.h
399
#define IMR_CPWM2_8723B
BIT9
/* CPU power Mode exchange INT Status, Write 1 clear */
428
#define IMR_TXFOVW_8723B
BIT9
/* Transmit FIFO Overflow */
H
A
D
odm_debug.h
70
#define ODM_COMP_RATE_ADAPTIVE
BIT9
H
A
D
odm_RegDefine11N.h
160
#define ODM_BIT_CCK_RPT_FORMAT_11N
BIT9
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/
H
A
D
Hal8723BReg.h
394
#define IMR_CPWM2_8723B
BIT9
/* CPU power Mode exchange INT Status, Write 1 clear */
423
#define IMR_TXFOVW_8723B
BIT9
/* Transmit FIFO Overflow */
H
A
D
odm_RegDefine11N.h
158
#define ODM_BIT_CCK_RPT_FORMAT_11N
BIT9
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/
H
A
D
rtl819x_Qos.h
19
#define
BIT9
0x00000200
macro
/kernel/linux/linux-6.6/drivers/staging/rtl8192e/
H
A
D
rtl819x_Qos.h
19
#define
BIT9
0x00000200
macro
/kernel/linux/linux-5.10/include/uapi/linux/
H
A
D
synclink.h
28
#define
BIT9
0x0200
macro
/kernel/linux/linux-6.6/include/uapi/linux/
H
A
D
synclink.h
28
#define
BIT9
0x0200
macro
/kernel/linux/patches/linux-6.6/prebuilts/usr/include/linux/
H
A
D
synclink.h
32
#define
BIT9
0x0200
macro
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
H
A
D
synclink.h
19
#define
BIT9
0x0200
macro
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/
H
A
D
synclink.h
32
#define
BIT9
0x0200
macro
/kernel/linux/linux-5.10/drivers/tty/
H
A
D
synclink.c
562
#define MISCSTATUS_DSR_LATCHED
BIT9
585
#define SICR_DSR_ACTIVE
BIT9
587
#define SICR_DSR (
BIT9
|BIT8)
1595
usc_OutDmaReg( info, CDIR,
BIT9
| BIT1 );
in mgsl_isr_receive_dma()
1704
else if ( (DmaVector&(BIT10|
BIT9
)) == BIT10)
in mgsl_interrupt()
4603
RegValue |=
BIT9
;
in usc_set_sdlc_mode()
4605
RegValue |= ( BIT12 | BIT10 |
BIT9
);
in usc_set_sdlc_mode()
4675
RegValue |=
BIT9
| BIT8;
in usc_set_sdlc_mode()
4677
RegValue |= ( BIT12 | BIT10 |
BIT9
| BIT8);
in usc_set_sdlc_mode()
4840
case HDLC_ENCODING_BIPHASE_SPACE: RegValue |=
BIT9
; brea
in usc_set_sdlc_mode()
[all...]
H
A
D
synclink_gt.c
390
#define IRQ_RXIDLE
BIT9
/* HDLC */
391
#define IRQ_RXBREAK
BIT9
/* async */
4071
val |=
BIT9
;
in async_mode()
4111
val |=
BIT9
;
in async_mode()
4234
case HDLC_CRC_16_CCITT: val |=
BIT9
; break;
in sync_mode()
4235
case HDLC_CRC_32_CCITT: val |=
BIT9
+ BIT8; break;
in sync_mode()
4307
case HDLC_CRC_16_CCITT: val |=
BIT9
; break;
in sync_mode()
4308
case HDLC_CRC_32_CCITT: val |=
BIT9
+ BIT8; break;
in sync_mode()
4951
if (!(*(src+1) & (
BIT9
+ BIT8))) {
in loopback_test_rx()
/kernel/linux/linux-6.6/drivers/scsi/
H
A
D
dc395x.h
67
#define
BIT9
0x00000200
macro
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