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Searched refs:BIT28 (Results 1 - 25 of 36) sorted by relevance

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/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
H A Dodm_DynamicBBPowerSaving.c70 PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x0); /* Reg818[28]= 1'b0 */ in ODM_RF_Saving()
71 PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x1); /* Reg818[28]= 1'b1 */ in ODM_RF_Saving()
77 PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x0); in ODM_RF_Saving()
H A DHalHWImg8723B_BB.c284 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
318 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
321 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
553 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
586 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
589 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
H A DHalHWImg8723B_MAC.c255 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
286 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
289 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
H A DHalHWImg8723B_RF.c286 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
320 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
323 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
H A DHal8723BReg.h388 #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/
H A Dodm_DynamicBBPowerSaving.c70 PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x0); /* Reg818[28]= 1'b0 */ in ODM_RF_Saving()
71 PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x1); /* Reg818[28]= 1'b1 */ in ODM_RF_Saving()
77 PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x0); in ODM_RF_Saving()
H A DHalHWImg8723B_MAC.c206 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
237 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
240 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
H A DHalHWImg8723B_BB.c236 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
270 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
273 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
498 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
531 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
534 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
H A DHalHWImg8723B_RF.c237 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
271 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
274 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
H A DHalPhyRf_8723B.c96 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32); in setIqkMatrix_8723B()
113 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00); in setIqkMatrix_8723B()
452 !(regEAC & BIT28) && in phy_PathA_IQK_8723B()
551 !(regEAC & BIT28) && in phy_PathA_RxIQK8723B()
735 !(regEAC & BIT28) && in phy_PathB_IQK_8723B()
830 !(regEAC & BIT28) && in phy_PathB_RxIQK8723B()
H A DHal8723BReg.h383 #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h59 #define BIT28 0x10000000 macro
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h59 #define BIT28 0x10000000 macro
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
H A Dhal_com_reg.h776 #define IMR_BCNDMAINT3 BIT28 /* Beacon DMA Interrupt 3 */
824 #define PHIMR_GTINT4 BIT28
875 #define UHIMR_GTINT4 BIT28
936 #define IMR_GTINT4_88E BIT28 /* When GTIMER4 expires, this bit is set to 1 */
1023 #define RCR_APP_PHYST_RXFF BIT28 /* PHY Status is appended before RX packet in RXFF */
1589 #define SDIO_HIMR_MCU_ERR_MSK BIT28
1615 #define SDIO_HISR_MCU_ERR BIT28
H A Drtl8723b_spec.h206 #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */
H A Dosdep_service.h49 #define BIT28 0x10000000 macro
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/
H A Drtl819x_Qos.h38 #define BIT28 0x10000000 macro
/kernel/linux/linux-6.6/drivers/staging/rtl8192e/
H A Drtl819x_Qos.h38 #define BIT28 0x10000000 macro
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/include/
H A Dosdep_service.h45 #define BIT28 0x10000000 macro
H A Drtl8723b_spec.h194 #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */
/kernel/linux/linux-5.10/include/uapi/linux/
H A Dsynclink.h47 #define BIT28 0x10000000 macro
/kernel/linux/linux-6.6/include/uapi/linux/
H A Dsynclink.h47 #define BIT28 0x10000000 macro
/kernel/linux/patches/linux-6.6/prebuilts/usr/include/linux/
H A Dsynclink.h51 #define BIT28 0x10000000 macro
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
H A Dsynclink.h38 #define BIT28 0x10000000 macro
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/
H A Dsynclink.h51 #define BIT28 0x10000000 macro

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