BIT12 (reference) in projects: kernel - OpenGrok search results

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Searched refs:BIT12 (Results 1 - 25 of 36) sorted by relevance

/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
H A D	r8192E_hw.h	`130 #define RCR_FILTER_MASK (BIT0 \| BIT1 \| BIT2 \| BIT3 \| BIT5 \| BIT12 \| \ 144 #define RCR_AICV BIT12 216 #define IMR_RXFOVW BIT12 243 #define TPPoll_StopVO BIT12 373 #define RRSR_MCS0 BIT12`
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A D	halbt_precomp.h	`43 #define BIT12 0x00001000 macro`
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A D	halbt_precomp.h	`43 #define BIT12 0x00001000 macro`
/kernel/linux/linux-6.6/drivers/staging/rtl8192e/rtl8192e/
H A D	r8192E_hw.h	`69 #define RCR_AICV BIT12 110 #define IMR_RXFOVW BIT12`
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
H A D	hal_com_reg.h	`620 #define RRSR_MCS0 BIT12 792 #define IMR_RXFOVW BIT12 /* Receive FIFO Overflow / 808 #define IMR_BcnInt_E BIT12 840 #define PHIMR_ATIM_CTW_END BIT12 891 #define UHIMR_CTW_END BIT12 916 #define UHIMR_ATIMEND BIT12 945 #define IMR_ATIMEND_88E BIT12 / CTWidnow End or ATIM Window End / 1039 #define RCR_ACF BIT12 / Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */`
H A D	rtl8723b_spec.h	`215 #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */`
H A D	osdep_service.h	`33 #define BIT12 0x00001000 macro`
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/
H A D	rtl819x_Qos.h	`22 #define BIT12 0x00001000 macro`
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
H A D	odm_debug.h	`73 #define ODM_COMP_DYNAMIC_PRICCA BIT12`
H A D	Hal8723BReg.h	`397 #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */`
/kernel/linux/linux-6.6/drivers/staging/rtl8192e/
H A D	rtl819x_Qos.h	`22 #define BIT12 0x00001000 macro`
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/include/
H A D	osdep_service.h	`29 #define BIT12 0x00001000 macro`
H A D	rtl8723b_spec.h	`203 #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */`
H A D	hal_com_reg.h	`559 #define RRSR_MCS0 BIT12 703 #define IMR_RXFOVW BIT12 /* Receive FIFO Overflow / 719 #define IMR_BcnInt_E BIT12 750 #define RCR_ACF BIT12 / Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */`
/kernel/linux/linux-5.10/include/uapi/linux/
H A D	synclink.h	`31 #define BIT12 0x1000 macro`
/kernel/linux/linux-6.6/include/uapi/linux/
H A D	synclink.h	`31 #define BIT12 0x1000 macro`
/kernel/linux/patches/linux-6.6/prebuilts/usr/include/linux/
H A D	synclink.h	`35 #define BIT12 0x1000 macro`
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
H A D	synclink.h	`22 #define BIT12 0x1000 macro`
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/
H A D	synclink.h	`35 #define BIT12 0x1000 macro`
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/
H A D	Hal8723BReg.h	`392 #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */`
/kernel/linux/linux-6.6/drivers/scsi/
H A D	dc395x.h	`64 #define BIT12 0x00001000 macro`
/kernel/linux/linux-5.10/drivers/tty/
H A D	synclink.c	559 #define MISCSTATUS_TXC BIT12 580 #define SICR_TXC_INACTIVE BIT12 581 #define SICR_TXC (BIT13\|BIT12) 1843 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) \| BIT13) \| BIT12)); in shutdown() 4529 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13\|BIT12)) \| BIT12)); in usc_set_sdlc_mode() 4563 RegValue \|= BIT12; in usc_set_sdlc_mode() 4605 RegValue \|= ( BIT12 \| BIT10 \| BIT9 ); in usc_set_sdlc_mode() 4677 RegValue \|= ( BIT12 \| BIT10 \| BIT9 \| BIT8); in usc_set_sdlc_mode() 4991 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue \|= BIT8 \| BIT12; brea in usc_set_sdlc_mode() [all...]
H A D	synclink_gt.c	387 #define IRQ_TXIDLE BIT12 4226 case HDLC_ENCODING_BIPHASE_MARK: val \|= BIT12; break; in sync_mode() 4227 case HDLC_ENCODING_BIPHASE_SPACE: val \|= BIT12 + BIT10; break; in sync_mode() 4228 case HDLC_ENCODING_BIPHASE_LEVEL: val \|= BIT12 + BIT11; break; in sync_mode() 4229 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val \|= BIT12 + BIT11 + BIT10; break; in sync_mode() 4299 case HDLC_ENCODING_BIPHASE_MARK: val \|= BIT12; break; in sync_mode() 4300 case HDLC_ENCODING_BIPHASE_SPACE: val \|= BIT12 + BIT10; break; in sync_mode() 4301 case HDLC_ENCODING_BIPHASE_LEVEL: val \|= BIT12 + BIT11; break; in sync_mode() 4302 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val \|= BIT12 + BIT11 + BIT10; break; in sync_mode()
/kernel/linux/linux-6.6/drivers/tty/
H A D	synclink_gt.c	382 #define IRQ_TXIDLE BIT12 4186 case HDLC_ENCODING_BIPHASE_MARK: val \|= BIT12; break; in sync_mode() 4187 case HDLC_ENCODING_BIPHASE_SPACE: val \|= BIT12 + BIT10; break; in sync_mode() 4188 case HDLC_ENCODING_BIPHASE_LEVEL: val \|= BIT12 + BIT11; break; in sync_mode() 4189 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val \|= BIT12 + BIT11 + BIT10; break; in sync_mode() 4259 case HDLC_ENCODING_BIPHASE_MARK: val \|= BIT12; break; in sync_mode() 4260 case HDLC_ENCODING_BIPHASE_SPACE: val \|= BIT12 + BIT10; break; in sync_mode() 4261 case HDLC_ENCODING_BIPHASE_LEVEL: val \|= BIT12 + BIT11; break; in sync_mode() 4262 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val \|= BIT12 + BIT11 + BIT10; break; in sync_mode()
/kernel/linux/linux-5.10/drivers/scsi/
H A D	dc395x.h	`64 #define BIT12 0x00001000 macro`

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