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Searched refs:BIT1 (Results 1 - 25 of 118) sorted by relevance

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/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h50 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
58 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
59 {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
60 {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
62 {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
71 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1,
[all...]
H A Dhal_com_reg.h609 #define RRSR_2M BIT1
634 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1
728 #define BW_OPMODE_5G BIT1
760 #define WOW_WOMEN BIT1 /* WoW function on or off. */
803 #define IMR_VODOK BIT1 /* AC_VO DMA Interrupt */
814 #define IMR_OCPINT BIT1
851 #define PHIMR_RDU BIT1 /* Receive Descriptor Unavailable */
869 #define PHIMR_OCPINT BIT1
902 #define UHIMR_RDU BIT1 /* Receive Descriptor Unavailable */
922 #define UHIMR_OCPINT BIT1
[all...]
H A Drtw_ht.h69 #define LDPC_HT_ENABLE_TX BIT1
74 #define STBC_HT_ENABLE_TX BIT1
79 #define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */
H A Dhal_phy.h39 #define ANT_DETECT_BY_RSSI BIT1
H A Drtl8723b_spec.h225 #define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h50 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
58 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
59 {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
60 {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
62 {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
71 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1,
[all...]
H A Drtw_ht.h65 #define LDPC_HT_ENABLE_TX BIT1
70 #define STBC_HT_ENABLE_TX BIT1
75 #define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */
H A Dhal_com_reg.h548 #define RRSR_2M BIT1
573 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1
671 #define WOW_WOMEN BIT1 /* WoW function on or off. */
714 #define IMR_VODOK BIT1 /* AC_VO DMA Interrupt */
725 #define IMR_OCPINT BIT1
762 #define RCR_APM BIT1 /* Accept physical match packet */
1279 #define SDIO_HIMR_AVAL_MSK BIT1
1301 #define SDIO_HISR_AVAL BIT1
1337 #define HCI_RESUME_PWR_RDY BIT1
1374 #define WL_HWPDN_SL BIT1 /* WiF
[all...]
H A Dhal_phy.h14 #define ANT_DETECT_BY_RSSI BIT1
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h29 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
57 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
66 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
69 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
173 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1,
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h29 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
57 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
66 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
69 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
173 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1,
[all...]
/kernel/linux/linux-6.6/drivers/scsi/
H A Ddc395x.h75 #define BIT1 0x00000002 macro
80 #define UNIT_INFO_CHANGED BIT1
86 #define SCSI_SUPPORT BIT1
122 #define RESET_DETECT BIT1
130 #define ABORTION BIT1
142 #define ABORT_DEV BIT1
166 #define SYNC_NEGO_DONE BIT1
593 #define GREATER_1G BIT1
/kernel/linux/linux-5.10/drivers/video/fbdev/via/
H A Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
325 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
346 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 in dvi_patch_skew_dvp_low()
[all...]
H A Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
563 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
608 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable()
652 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
654 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
674 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1); in integrated_lvds_enable()
746 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
/kernel/linux/linux-6.6/drivers/video/fbdev/via/
H A Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
325 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
346 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 in dvi_patch_skew_dvp_low()
[all...]
H A Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
561 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
606 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable()
650 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
652 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
672 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1); in integrated_lvds_enable()
744 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
148 #define RCR_APM BIT1
202 #define SCR_RxUseDK BIT1
227 #define IMR_VODOK BIT1
232 #define TPPoll_BEQ BIT1
272 #define AcmHw_BeqEn BIT1
280 #define AcmFw_ViqStatus BIT1
333 #define BW_OPMODE_5G BIT1
362 #define RRSR_2M BIT1
/kernel/linux/linux-6.6/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h72 #define RCR_APM BIT1
99 #define SCR_RxUseDK BIT1
121 #define IMR_VODOK BIT1
139 #define ACM_HW_BEQ_EN BIT1
182 #define RRSR_2M BIT1
/kernel/linux/linux-5.10/drivers/scsi/
H A Ddc395x.h75 #define BIT1 0x00000002 macro
80 #define UNIT_INFO_CHANGED BIT1
86 #define SCSI_SUPPORT BIT1
122 #define RESET_DETECT BIT1
130 #define ABORTION BIT1
142 #define ABORT_DEV BIT1
175 #define SYNC_NEGO_DONE BIT1
631 #define GREATER_1G BIT1
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
H A Dodm_DIG.h93 ODM_RESUME_DIG = BIT1
98 ODM_RESUME_CCKPD = BIT1
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h32 #define BIT1 0x00000002 macro
H A Dhalbtc8192e2ant.h13 #define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
H A Dhalbtc8821a2ant.h14 #define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h32 #define BIT1 0x00000002 macro
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/
H A Drtl819x_Qos.h11 #define BIT1 0x00000002 macro

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