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/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h44 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
49 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* Disable USB suspend */ \
51 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* Enable USB suspend */ \
52 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \
55 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
56 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0,
[all...]
H A Dhal_com_reg.h560 #define HSIMR_GPIO12_0_INT_EN BIT0
569 #define HSISR_GPIO12_0_INT BIT0
608 #define RRSR_1M BIT0
633 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0
759 #define WOW_PMEN BIT0 /* Power management Enable. */
804 #define IMR_ROK BIT0 /* Receive DMA OK Interrupt */
815 #define IMR_WLANOFF BIT0
852 #define PHIMR_ROK BIT0 /* Receive DMA OK Interrupt */
903 #define UHIMR_ROK BIT0 /* Receive DMA OK Interrupt */
957 #define IMR_ROK_88E BIT0 /* Receiv
[all...]
H A Drtw_ht.h68 #define LDPC_HT_ENABLE_RX BIT0
73 #define STBC_HT_ENABLE_RX BIT0
78 #define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h44 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
49 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* Disable USB suspend */ \
51 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* Enable USB suspend */ \
52 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \
55 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
56 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0,
[all...]
H A Drtw_ht.h64 #define LDPC_HT_ENABLE_RX BIT0
69 #define STBC_HT_ENABLE_RX BIT0
74 #define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */
H A Dhal_com_reg.h524 #define HSISR_GPIO12_0_INT BIT0
547 #define RRSR_1M BIT0
572 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0
670 #define WOW_PMEN BIT0 /* Power management Enable. */
715 #define IMR_ROK BIT0 /* Receive DMA OK Interrupt */
726 #define IMR_WLANOFF BIT0
763 #define RCR_AAP BIT0 /* Accept all unicast packet */
1278 #define SDIO_HIMR_RX_REQUEST_MSK BIT0
1300 #define SDIO_HISR_RX_REQUEST BIT0
1338 #define HCI_SUS_CTRL BIT0
[all...]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h38 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
41 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
51 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
247 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h38 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
41 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
51 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
247 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT
[all...]
/kernel/linux/linux-5.10/drivers/video/fbdev/via/
H A Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
395 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 in viafb_dvi_enable()
[all...]
H A Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
563 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
585 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); in viafb_lcd_set_mode()
652 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
654 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
661 viafb_write_reg_mask(CR91, VIACR, 0, BIT0); in integrated_lvds_enable()
670 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0); in integrated_lvds_enable()
746 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
846 bdithering = BIT0; in fill_lcd_format()
[all...]
H A Dvia_utility.c152 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_set_gamma_table()
169 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_set_gamma_table()
207 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_get_gamma_table()
/kernel/linux/linux-6.6/drivers/video/fbdev/via/
H A Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
395 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 in viafb_dvi_enable()
[all...]
H A Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
561 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
583 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); in viafb_lcd_set_mode()
650 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
652 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
659 viafb_write_reg_mask(CR91, VIACR, 0, BIT0); in integrated_lvds_enable()
668 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0); in integrated_lvds_enable()
744 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
844 bdithering = BIT0; in fill_lcd_format()
[all...]
H A Dvia_utility.c152 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_set_gamma_table()
169 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_set_gamma_table()
207 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_get_gamma_table()
/kernel/linux/linux-6.6/drivers/scsi/
H A Ddc395x.h76 #define BIT0 0x00000001 macro
79 #define UNIT_ALLOCATED BIT0
85 #define DASD_SUPPORT BIT0
121 #define RESET_DEV BIT0
126 #define ABORT_DEV_ BIT0
129 #define SRB_OK BIT0
143 #define AUTO_REQSENSE BIT0
165 #define SYNC_NEGO_ENABLE BIT0
592 #define MORE2_DRV BIT0
/kernel/linux/linux-5.10/drivers/scsi/
H A Ddc395x.h76 #define BIT0 0x00000001 macro
79 #define UNIT_ALLOCATED BIT0
85 #define DASD_SUPPORT BIT0
121 #define RESET_DEV BIT0
126 #define ABORT_DEV_ BIT0
129 #define SRB_OK BIT0
143 #define AUTO_REQSENSE BIT0
174 #define SYNC_NEGO_ENABLE BIT0
630 #define MORE2_DRV BIT0
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
149 #define RCR_AAP BIT0
201 #define SCR_TxUseDK BIT0
228 #define IMR_ROK BIT0
231 #define TPPoll_BKQ BIT0
271 #define AcmHw_HwEn BIT0
279 #define AcmFw_BeqStatus BIT0
332 #define BW_OPMODE_11J BIT0
361 #define RRSR_1M BIT0
/kernel/linux/linux-6.6/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_hw.h73 #define RCR_AAP BIT0
98 #define SCR_TxUseDK BIT0
122 #define IMR_ROK BIT0
181 #define RRSR_1M BIT0
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
H A Dodm_DIG.h92 ODM_PAUSE_DIG = BIT0,
97 ODM_PAUSE_CCKPD = BIT0,
H A DHalBtc8723b1Ant.h15 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
18 (((_BT_INFO_EXT_&BIT0)) ? true : false)
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/core/
H A Drtw_odm.c14 /* BIT0 */"ODM_COMP_DIG",
51 /* BIT0 */"ODM_BB_DIG",
103 (BIT0 << i) & dbg_comp ? '+' : ' ', in rtw_odm_dbg_comp_msg()
142 (BIT0 << i) & ability ? '+' : ' ', i, in rtw_odm_ability_msg()
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbtc8723b1ant.h14 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
17 (((_BT_INFO_EXT_&BIT0)) ? true : false)
H A Dhalbtc8821a1ant.h15 #define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
18 (((_BT_INFO_EXT_&BIT0)) ? true : false)
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/
H A DHalBtc8723b1Ant.h15 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
18 (((_BT_INFO_EXT_ & BIT0)) ? true : false)
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbtc8723b1ant.h14 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
17 (((_BT_INFO_EXT_&BIT0)) ? true : false)

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