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Searched refs:BIOS_CMD_TABLE_PARA_REVISION (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table.c46 #define BIOS_CMD_TABLE_PARA_REVISION(command)\ macro
121 BIOS_CMD_TABLE_PARA_REVISION(DIGxEncoderControl); in init_dig_encoder_control()
155 if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG1EncoderControl)) in init_encoder_control_dig_v1()
160 if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG2EncoderControl)) in init_encoder_control_dig_v1()
952 switch (BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)) { in init_set_pixel_clock()
967 BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)); in init_set_pixel_clock()
1297 switch (BIOS_CMD_TABLE_PARA_REVISION(EnableSpreadSpectrumOnPPLL)) { in init_enable_spread_spectrum_on_ppll()
1312 BIOS_CMD_TABLE_PARA_REVISION(EnableSpreadSpectrumOnPPLL)); in init_enable_spread_spectrum_on_ppll()
1500 switch (BIOS_CMD_TABLE_PARA_REVISION(AdjustDisplayPll)) { in init_adjust_display_pll()
1509 BIOS_CMD_TABLE_PARA_REVISION(AdjustDisplayPl in init_adjust_display_pll()
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H A Dcommand_table2.c60 #define BIOS_CMD_TABLE_PARA_REVISION(fname)\ macro
99 BIOS_CMD_TABLE_PARA_REVISION(digxencodercontrol); in init_dig_encoder_control()
337 switch (BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)) { in init_set_pixel_clock()
343 BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)); in init_set_pixel_clock()
482 BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming); in init_set_crtc_timing()
602 switch (BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)) { in init_enable_crtc()
608 BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)); in init_enable_crtc()
664 switch (BIOS_CMD_TABLE_PARA_REVISION(externalencodercontrol)) { in init_external_encoder_control()
704 switch (BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating)) { in init_enable_disp_power_gating()
711 BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergatin in init_enable_disp_power_gating()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table.c46 #define BIOS_CMD_TABLE_PARA_REVISION(command)\ macro
121 BIOS_CMD_TABLE_PARA_REVISION(DIGxEncoderControl); in init_dig_encoder_control()
155 if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG1EncoderControl)) in init_encoder_control_dig_v1()
160 if (1 == BIOS_CMD_TABLE_PARA_REVISION(DIG2EncoderControl)) in init_encoder_control_dig_v1()
953 switch (BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)) { in init_set_pixel_clock()
968 BIOS_CMD_TABLE_PARA_REVISION(SetPixelClock)); in init_set_pixel_clock()
1298 switch (BIOS_CMD_TABLE_PARA_REVISION(EnableSpreadSpectrumOnPPLL)) { in init_enable_spread_spectrum_on_ppll()
1313 BIOS_CMD_TABLE_PARA_REVISION(EnableSpreadSpectrumOnPPLL)); in init_enable_spread_spectrum_on_ppll()
1501 switch (BIOS_CMD_TABLE_PARA_REVISION(AdjustDisplayPll)) { in init_adjust_display_pll()
1510 BIOS_CMD_TABLE_PARA_REVISION(AdjustDisplayPl in init_adjust_display_pll()
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H A Dcommand_table2.c58 #define BIOS_CMD_TABLE_PARA_REVISION(fname)\ macro
97 BIOS_CMD_TABLE_PARA_REVISION(digxencodercontrol); in init_dig_encoder_control()
405 switch (BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)) { in init_set_pixel_clock()
411 BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)); in init_set_pixel_clock()
548 BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming); in init_set_crtc_timing()
668 switch (BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)) { in init_enable_crtc()
674 BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)); in init_enable_crtc()
730 switch (BIOS_CMD_TABLE_PARA_REVISION(externalencodercontrol)) { in init_external_encoder_control()
770 switch (BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating)) { in init_enable_disp_power_gating()
777 BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergatin in init_enable_disp_power_gating()
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