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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_link_encoder.h227 #define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
228 type DIG_ENABLE;\
229 type DIG_HPD_SELECT;\
230 type DIG_MODE;\
231 type DIG_FE_SOURCE_SELECT;\
232 type DIG_CLOCK_PATTERN;\
233 type DPHY_BYPASS;\
234 type DPHY_ATEST_SEL_LANE0;\
235 type DPHY_ATEST_SEL_LANE1;\
236 type DPHY_ATEST_SEL_LANE
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H A Ddcn10_dpp.h479 #define TF_REG_FIELD_LIST(type) \
480 type EXT_OVERSCAN_LEFT; \
481 type EXT_OVERSCAN_RIGHT; \
482 type EXT_OVERSCAN_BOTTOM; \
483 type EXT_OVERSCAN_TOP; \
484 type OTG_H_BLANK_START; \
485 type OTG_H_BLANK_END; \
486 type OTG_V_BLANK_START; \
487 type OTG_V_BLANK_END; \
488 type PIXEL_DEPT
[all...]
H A Ddcn10_hubbub.h181 #define HUBBUB_REG_FIELD_LIST_DCN32(type) \
182 type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE;\
183 type DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE;\
184 type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST;\
185 type DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE;\
186 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A;\
187 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B;\
188 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C;\
189 type DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D;\
190 type DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_
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H A Ddcn10_stream_encoder.h353 #define SE_REG_FIELD_LIST_DCN1_0(type) \
354 type AFMT_GENERIC_INDEX;\
355 type AFMT_GENERIC_HB0;\
356 type AFMT_GENERIC_HB1;\
357 type AFMT_GENERIC_HB2;\
358 type AFMT_GENERIC_HB3;\
359 type AFMT_GENERIC_LOCK_STATUS;\
360 type AFMT_GENERIC_CONFLICT;\
361 type AFMT_GENERIC_CONFLICT_CLR;\
362 type AFMT_GENERIC0_FRAME_UPDATE_PENDIN
[all...]
H A Ddcn10_optc.h339 #define TG_REG_FIELD_LIST_DCN1_0(type) \
340 type VSTARTUP_START;\
341 type VUPDATE_OFFSET;\
342 type VUPDATE_WIDTH;\
343 type VREADY_OFFSET;\
344 type OTG_BLANK_DATA_EN;\
345 type OTG_BLANK_DE_MODE;\
346 type OTG_CURRENT_BLANK_STATE;\
347 type OTG_MASTER_UPDATE_LOCK;\
348 type UPDATE_LOCK_STATU
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_link_encoder.h218 #define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
219 type DIG_ENABLE;\
220 type DIG_HPD_SELECT;\
221 type DIG_MODE;\
222 type DIG_FE_SOURCE_SELECT;\
223 type DPHY_BYPASS;\
224 type DPHY_ATEST_SEL_LANE0;\
225 type DPHY_ATEST_SEL_LANE1;\
226 type DPHY_ATEST_SEL_LANE2;\
227 type DPHY_ATEST_SEL_LANE
[all...]
H A Ddcn10_dpp.h473 #define TF_REG_FIELD_LIST(type) \
474 type EXT_OVERSCAN_LEFT; \
475 type EXT_OVERSCAN_RIGHT; \
476 type EXT_OVERSCAN_BOTTOM; \
477 type EXT_OVERSCAN_TOP; \
478 type OTG_H_BLANK_START; \
479 type OTG_H_BLANK_END; \
480 type OTG_V_BLANK_START; \
481 type OTG_V_BLANK_END; \
482 type PIXEL_DEPT
[all...]
H A Ddcn10_optc.h326 #define TG_REG_FIELD_LIST_DCN1_0(type) \
327 type VSTARTUP_START;\
328 type VUPDATE_OFFSET;\
329 type VUPDATE_WIDTH;\
330 type VREADY_OFFSET;\
331 type OTG_BLANK_DATA_EN;\
332 type OTG_BLANK_DE_MODE;\
333 type OTG_CURRENT_BLANK_STATE;\
334 type OTG_MASTER_UPDATE_LOCK;\
335 type UPDATE_LOCK_STATU
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H A Ddcn10_hubbub.h188 #define DCN_HUBBUB_REG_FIELD_LIST(type) \
189 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
190 type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\
191 type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\
192 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\
193 type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\
194 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\
195 type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\
196 type DCHUBBUB_ARB_SAT_LEVEL;\
197 type DCHUBBUB_ARB_MIN_REQ_OUTSTAN
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H A Ddcn10_stream_encoder.h332 #define SE_REG_FIELD_LIST_DCN1_0(type) \
333 type AFMT_GENERIC_INDEX;\
334 type AFMT_GENERIC_HB0;\
335 type AFMT_GENERIC_HB1;\
336 type AFMT_GENERIC_HB2;\
337 type AFMT_GENERIC_HB3;\
338 type AFMT_GENERIC_LOCK_STATUS;\
339 type AFMT_GENERIC_CONFLICT;\
340 type AFMT_GENERIC_CONFLICT_CLR;\
341 type AFMT_GENERIC0_FRAME_UPDATE_PENDIN
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/kernel/linux/linux-6.6/drivers/net/ethernet/microchip/vcap/
H A Dvcap_model_kunit.c19 .type = VCAP_FIELD_U32,
24 .type = VCAP_FIELD_BIT,
29 .type = VCAP_FIELD_U32,
34 .type = VCAP_FIELD_U32,
39 .type = VCAP_FIELD_U32,
44 .type = VCAP_FIELD_U32,
49 .type = VCAP_FIELD_BIT,
54 .type = VCAP_FIELD_U32,
59 .type = VCAP_FIELD_U32,
64 .type
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_vcap_ag_api.c19 .type = VCAP_FIELD_BIT,
24 .type = VCAP_FIELD_BIT,
29 .type = VCAP_FIELD_U32,
34 .type = VCAP_FIELD_U32,
39 .type = VCAP_FIELD_U32,
44 .type = VCAP_FIELD_U72,
49 .type = VCAP_FIELD_BIT,
54 .type = VCAP_FIELD_BIT,
59 .type = VCAP_FIELD_U32,
64 .type
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
H A Dirq-s3c24xx.c42 unsigned int type; member
136 static int s3c_irq_type(struct irq_data *data, unsigned int type) in s3c_irq_type() argument
138 switch (type) { in s3c_irq_type()
151 pr_err("No such irq type %d\n", type); in s3c_irq_type()
162 unsigned int type) in s3c_irqext_type_set()
171 /* Set the external interrupt to pointed trigger type */ in s3c_irqext_type_set()
172 switch (type) in s3c_irqext_type_set()
199 pr_err("No such irq type %d\n", type); in s3c_irqext_type_set()
158 s3c_irqext_type_set(void __iomem *gpcon_reg, void __iomem *extint_reg, unsigned long gpcon_offset, unsigned long extint_offset, unsigned int type) s3c_irqext_type_set() argument
210 s3c_irqext_type(struct irq_data *data, unsigned int type) s3c_irqext_type() argument
239 s3c_irqext0_type(struct irq_data *data, unsigned int type) s3c_irqext0_type() argument
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_vcap_ag_api.c11 .type = VCAP_FIELD_BIT,
16 .type = VCAP_FIELD_U32,
21 .type = VCAP_FIELD_U32,
26 .type = VCAP_FIELD_BIT,
31 .type = VCAP_FIELD_BIT,
36 .type = VCAP_FIELD_BIT,
41 .type = VCAP_FIELD_BIT,
46 .type = VCAP_FIELD_BIT,
51 .type = VCAP_FIELD_BIT,
56 .type
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dwb.h424 #define DWBC_REG_FIELD_LIST_DCN3_0(type) \
425 type DWB_ENABLE;\
426 type DISPCLK_R_DWB_GATE_DIS;\
427 type DISPCLK_G_DWB_GATE_DIS;\
428 type DWB_TEST_CLK_SEL;\
429 type DWBSCL_LUT_MEM_PWR_FORCE;\
430 type DWBSCL_LUT_MEM_PWR_DIS;\
431 type DWBSCL_LUT_MEM_PWR_STATE;\
432 type DWBSCL_LB_MEM_PWR_FORCE;\
433 type DWBSCL_LB_MEM_PWR_DI
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dwb.h409 #define DWBC_REG_FIELD_LIST_DCN3_0(type) \
410 type DWB_ENABLE;\
411 type DISPCLK_R_DWB_GATE_DIS;\
412 type DISPCLK_G_DWB_GATE_DIS;\
413 type DWB_TEST_CLK_SEL;\
414 type DWBSCL_LUT_MEM_PWR_FORCE;\
415 type DWBSCL_LUT_MEM_PWR_DIS;\
416 type DWBSCL_LUT_MEM_PWR_STATE;\
417 type DWBSCL_LB_MEM_PWR_FORCE;\
418 type DWBSCL_LB_MEM_PWR_DI
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/kernel/linux/linux-5.10/net/ieee802154/
H A Dnl_policy.c15 [IEEE802154_ATTR_DEV_NAME] = { .type = NLA_STRING, },
16 [IEEE802154_ATTR_DEV_INDEX] = { .type = NLA_U32, },
17 [IEEE802154_ATTR_PHY_NAME] = { .type = NLA_STRING, },
19 [IEEE802154_ATTR_STATUS] = { .type = NLA_U8, },
20 [IEEE802154_ATTR_SHORT_ADDR] = { .type = NLA_U16, },
21 [IEEE802154_ATTR_HW_ADDR] = { .type = NLA_HW_ADDR, },
22 [IEEE802154_ATTR_PAN_ID] = { .type = NLA_U16, },
23 [IEEE802154_ATTR_CHANNEL] = { .type = NLA_U8, },
24 [IEEE802154_ATTR_BCN_ORD] = { .type = NLA_U8, },
25 [IEEE802154_ATTR_SF_ORD] = { .type
[all...]
/kernel/linux/linux-6.6/net/ieee802154/
H A Dnl_policy.c15 [IEEE802154_ATTR_DEV_NAME] = { .type = NLA_STRING, },
16 [IEEE802154_ATTR_DEV_INDEX] = { .type = NLA_U32, },
17 [IEEE802154_ATTR_PHY_NAME] = { .type = NLA_STRING, },
19 [IEEE802154_ATTR_STATUS] = { .type = NLA_U8, },
20 [IEEE802154_ATTR_SHORT_ADDR] = { .type = NLA_U16, },
21 [IEEE802154_ATTR_HW_ADDR] = { .type = NLA_HW_ADDR, },
22 [IEEE802154_ATTR_PAN_ID] = { .type = NLA_U16, },
23 [IEEE802154_ATTR_CHANNEL] = { .type = NLA_U8, },
24 [IEEE802154_ATTR_BCN_ORD] = { .type = NLA_U8, },
25 [IEEE802154_ATTR_SF_ORD] = { .type
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.h116 #define DCCG_REG_FIELD_LIST(type) \
117 type DPPCLK0_DTO_PHASE;\
118 type DPPCLK0_DTO_MODULO;\
119 type DPPCLK_DTO_ENABLE[6];\
120 type DPPCLK_DTO_DB_EN[6];\
121 type REFCLK_CLOCK_EN;\
122 type REFCLK_SRC_SEL;\
123 type DISPCLK_STEP_DELAY;\
124 type DISPCLK_STEP_SIZE;\
125 type DISPCLK_FREQ_RAMP_DON
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/kernel/linux/linux-5.10/include/uapi/linux/
H A Dv4l2-dv-timings.h35 .type = V4L2_DV_BT_656_1120, \
45 .type = V4L2_DV_BT_656_1120, \
55 .type = V4L2_DV_BT_656_1120, \
66 .type = V4L2_DV_BT_656_1120, \
76 .type = V4L2_DV_BT_656_1120, \
85 .type = V4L2_DV_BT_656_1120, \
94 .type = V4L2_DV_BT_656_1120, \
103 .type = V4L2_DV_BT_656_1120, \
113 .type = V4L2_DV_BT_656_1120, \
122 .type
[all...]
/kernel/linux/linux-6.6/include/uapi/linux/
H A Dv4l2-dv-timings.h26 .type = V4L2_DV_BT_656_1120, \
36 .type = V4L2_DV_BT_656_1120, \
46 .type = V4L2_DV_BT_656_1120, \
57 .type = V4L2_DV_BT_656_1120, \
67 .type = V4L2_DV_BT_656_1120, \
76 .type = V4L2_DV_BT_656_1120, \
85 .type = V4L2_DV_BT_656_1120, \
94 .type = V4L2_DV_BT_656_1120, \
104 .type = V4L2_DV_BT_656_1120, \
113 .type
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/kernel/linux/patches/linux-6.6/prebuilts/usr/include/linux/
H A Dv4l2-dv-timings.h26 #define V4L2_DV_BT_CEA_640X480P59_94 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 1) \
28 #define V4L2_DV_BT_CEA_720X480I59_94 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 6) \
30 #define V4L2_DV_BT_CEA_720X480P59_94 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 2) \
32 #define V4L2_DV_BT_CEA_720X576I50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 21) \
34 #define V4L2_DV_BT_CEA_720X576P50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 17) \
36 #define V4L2_DV_BT_CEA_1280X720P24 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \
38 #define V4L2_DV_BT_CEA_1280X720P25 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \
40 #define V4L2_DV_BT_CEA_1280X720P30 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \
42 #define V4L2_DV_BT_CEA_1280X720P50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \
44 #define V4L2_DV_BT_CEA_1280X720P60 {.type
[all...]
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
H A Dv4l2-dv-timings.h16 .type = V4L2_DV_BT_656_1120, \
23 .type = V4L2_DV_BT_656_1120, \
32 .type = V4L2_DV_BT_656_1120, \
40 .type = V4L2_DV_BT_656_1120, \
49 .type = V4L2_DV_BT_656_1120, \
57 .type = V4L2_DV_BT_656_1120, \
65 .type = V4L2_DV_BT_656_1120, \
73 .type = V4L2_DV_BT_656_1120, \
82 .type = V4L2_DV_BT_656_1120, \
90 .type
[all...]
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/
H A Dv4l2-dv-timings.h26 #define V4L2_DV_BT_CEA_640X480P59_94 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 1) \
28 #define V4L2_DV_BT_CEA_720X480I59_94 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 6) \
30 #define V4L2_DV_BT_CEA_720X480P59_94 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 2) \
32 #define V4L2_DV_BT_CEA_720X576I50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 21) \
34 #define V4L2_DV_BT_CEA_720X576P50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 17) \
36 #define V4L2_DV_BT_CEA_1280X720P24 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \
38 #define V4L2_DV_BT_CEA_1280X720P25 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \
40 #define V4L2_DV_BT_CEA_1280X720P30 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \
42 #define V4L2_DV_BT_CEA_1280X720P50 {.type = V4L2_DV_BT_656_1120, V4L2_INIT_BT_TIMINGS(1280, 720, 0, V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \
44 #define V4L2_DV_BT_CEA_1280X720P60 {.type
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dsc.h263 #define DSC_FIELD_LIST_DCN20(type)\
264 type DSC_CLOCK_EN; \
265 type DSC_DISPCLK_R_GATE_DIS; \
266 type DSC_DSCCLK_R_GATE_DIS; \
267 type DSC_DBG_EN; \
268 type DSC_TEST_CLOCK_MUX_SEL; \
269 type ICH_RESET_AT_END_OF_LINE; \
270 type NUMBER_OF_SLICES_PER_LINE; \
271 type ALTERNATE_ICH_ENCODING_EN; \
272 type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTIO
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