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/drivers/hdf_core/adapter/khdf/linux/platform/mipi_dsi/
H A Dmipi_tx_reg.h24 /* Define the struct bits */
28 } bits; member
36 /* Define the struct bits */
41 } bits; member
49 /* Define the struct bits */
53 } bits; member
61 /* Define the struct bits */
67 } bits; member
75 /* Define the struct bits */
81 } bits; member
97 } bits; global() member
109 } bits; global() member
121 } bits; global() member
147 } bits; global() member
159 } bits; global() member
171 } bits; global() member
183 } bits; global() member
195 } bits; global() member
207 } bits; global() member
219 } bits; global() member
231 } bits; global() member
243 } bits; global() member
255 } bits; global() member
267 } bits; global() member
279 } bits; global() member
307 } bits; global() member
322 } bits; global() member
336 } bits; global() member
354 } bits; global() member
366 } bits; global() member
378 } bits; global() member
391 } bits; global() member
405 } bits; global() member
419 } bits; global() member
434 } bits; global() member
448 } bits; global() member
463 } bits; global() member
487 } bits; global() member
500 } bits; global() member
514 } bits; global() member
546 } bits; global() member
578 } bits; global() member
610 } bits; global() member
642 } bits; global() member
654 } bits; global() member
686 } bits; global() member
723 } bits; global() member
735 } bits; global() member
747 } bits; global() member
759 } bits; global() member
771 } bits; global() member
783 } bits; global() member
801 } bits; global() member
821 } bits; global() member
832 } bits; global() member
842 } bits; global() member
859 } bits; global() member
[all...]
H A Dmipi_tx_hi35xx.c438 phyCtx->hactDet = g_mipiTxRegsVa->HORI0_DET.bits.hact_det; in MipiTxDrvGetDevStatus()
439 phyCtx->hallDet = g_mipiTxRegsVa->HORI0_DET.bits.hline_det; in MipiTxDrvGetDevStatus()
440 phyCtx->hbpDet = g_mipiTxRegsVa->HORI1_DET.bits.hbp_det; in MipiTxDrvGetDevStatus()
441 phyCtx->hsaDet = g_mipiTxRegsVa->HORI1_DET.bits.hsa_det; in MipiTxDrvGetDevStatus()
442 phyCtx->vactDet = g_mipiTxRegsVa->VERT_DET.bits.vact_det; in MipiTxDrvGetDevStatus()
443 phyCtx->vallDet = g_mipiTxRegsVa->VERT_DET.bits.vall_det; in MipiTxDrvGetDevStatus()
444 phyCtx->vsaDet = g_mipiTxRegsVa->VSA_DET.bits.vsa_det; in MipiTxDrvGetDevStatus()
616 } while (cmdPktStatus.bits.gen_cmd_empty == 0); in MipiTxWaitCmdFifoEmpty()
634 } while (cmdPktStatus.bits.gen_pld_w_empty == 0); in MipiTxWaitWriteFifoEmpty()
655 } while (cmdPktStatus.bits in MipiTxWaitWriteFifoNotFull()
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/drivers/hdf_core/framework/support/platform/include/hdmi/
H A Dhdmi_scdc.h75 } bits; member
99 } bits; member
111 } bits; member
127 } bits; member
141 } bits; member
158 } bits; member
192 } bits; member
212 } bits; member
224 } bits; member
234 uint16_t chErrCntLower : 8; /* Channel 0/1/2 Erroe Count bits
237 } bits; global() member
249 } bits; global() member
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H A Dhdmi_infoframe.h395 } bits; member
404 } bits; member
414 } bits; member
H A Dhdmi_core.h74 uint32_t deepColor10bits : 1; /* bit14: support deep color 10 bits */
75 uint32_t deepColor12bits : 1; /* bit15: support deep color 12 bits */
76 uint32_t deepColor16bits : 1; /* bit16: support deep color 16 bits */
80 } bits; member
/drivers/hdf_core/framework/test/unittest/platform/common/
H A Dspi_test.c168 static int32_t SpiCmpMemByBits(uint8_t *wbuf, uint8_t *rbuf, uint32_t len, uint8_t bits) in SpiCmpMemByBits() argument
174 if (bits < SPI_TEST_4BITS) { in SpiCmpMemByBits()
175 bits = SPI_TEST_4BITS; in SpiCmpMemByBits()
176 } else if (bits > SPI_TEST_16BITS) { in SpiCmpMemByBits()
177 bits = SPI_TEST_16BITS; in SpiCmpMemByBits()
181 if (bits <= SPI_TEST_8BITS) { in SpiCmpMemByBits()
182 vw = *((uint8_t *)(wbuf + i)) & (~(0xFFFF << bits)); in SpiCmpMemByBits()
183 vr = *((uint8_t *)(rbuf + i)) & (~(0xFFFF << bits)); in SpiCmpMemByBits()
185 vw = *((uint16_t *)(wbuf + i)) & (~(0xFFFF << bits)); in SpiCmpMemByBits()
186 vr = *((uint16_t *)(rbuf + i)) & (~(0xFFFF << bits)); in SpiCmpMemByBits()
[all...]
/drivers/hdf_core/framework/core/sec/include/
H A Dhdf_sec.h35 #define HDF_DECLARE_BITMAP(name, bits) \
36 uint64_t name[HDF_BITS_TO_LONGS(bits)]
/drivers/hdf_core/framework/support/platform/src/hdmi/
H A Dhdmi_core.c48 if (cntlr->cap.baseCap.bits.cec == 0) { in HdmiCecInit()
116 if (cntlr->cap.baseCap.bits.frl == 0) { in HdmiFrlInit()
150 if (cntlr->cap.baseCap.bits.hdcp == 0) { in HdmiHdcpInit()
188 if (cntlr->cap.baseCap.bits.hdr == 0) { in HdmiHdrInit()
241 if (cntlr->cap.baseCap.bits.scdc == 0) { in HdmiScdcInit()
567 if (HdmiFrlSupport(cntlr->frl) == true && cntlr->cap.baseCap.bits.frl > 0) { in HdmiCntlrModeSelect()
571 if (cntlr->cap.baseCap.bits.scdc > 0) { in HdmiCntlrModeSelect()
584 if (cntlr->cap.baseCap.bits.scdc > 0 && HdmiEdidScdcSupport(cntlr->hdmi) == true) { in HdmiCntlrModeSelect()
722 if (cntlr->cap.baseCap.bits.hdr > 0 && cntlr->cap.baseCap.bits in HdmiCntlrStart()
[all...]
H A Dhdmi_frl.c142 cfg.bits.frlRate = frl->info.curFrlRate; in HdmiFrlSetTrainRate()
143 cfg.bits.ffeLevels = HDMI_FRL_TXFFE_MODE_0; in HdmiFrlSetTrainRate()
156 cntlr->cap.baseCap.bits.hdmi21 == 0 || in HdmiFrlCheckFrlCapability()
157 cntlr->cap.baseCap.bits.frl == 0 || in HdmiFrlCheckFrlCapability()
276 if ((cfg.bits.frlMax > 0 && cfg.bits.dscFrlMax == 0) || in HdmiFrlIsCtsMode()
277 (cfg.bits.frlMax == 0 && cfg.bits.dscFrlMax > 0)) { in HdmiFrlIsCtsMode()
420 if (testCfg.bits.fltNoTimeout > 0) { in HdmiFrlConfigAndStartTraining()
H A Dhdmi_scdc.c228 cfg.bits.scramblingEnable = 1; in HdmiScdcScrambleSet()
231 cfg.bits.tmdsBitClockRatio = 1; in HdmiScdcScrambleSet()
256 scramble->sinkScramble = (status.bits.scramblingStatus ? true : false); in HdmiScdcScrambleGet()
263 scramble->tmdsBitClockRatio40 = (cfg.bits.tmdsBitClockRatio ? true : false); in HdmiScdcScrambleGet()
H A Dhdmi_cec.c1490 if (cntlr->cap.baseCap.bits.cecRc == 0) { in HdmiCecHandleUserControlPrtessedMsg()
1503 if (cntlr->cap.baseCap.bits.cecRc == 0) { in HdmiCecHandleUserControlReleasedMsg()
1690 if (cntlr->cap.baseCap.bits.cec == 0) { in HdmiCecReceivedMsg()
/drivers/hdf_core/framework/model/storage/src/mmc/
H A Dmmc_protocol.c123 /* [31:0] stuff bits. */ in MmcGoIdleState()
181 /* [31:0] stuff bits. */ in MmcAllSendCid()
208 /* [31:16] RCA, [15:0] stuff bits. */ in MmcSetRelativeAddr()
224 /* [31:16] RCA, [15:0] stuff bits. */ in MmcSelectCard()
286 /* [31:16] RCA, [15:0] stuff bits. */ in MmcSendStatus()
335 * SWITCH_ERROR bit in the status register and will not change the PARTITION_ACCESS bits. in MmcSwitch()
359 /* [31:16] RCA, [15:0] stuff bits */ in MmcAppCmd()
509 if (dev->state.bits.blockAddr == 0) { in MmcSendEraseStartCmd()
538 if (dev->state.bits.blockAddr == 0) { in MmcSendEraseEndCmd()
623 * finally it starts the erase process by issuing the ERASE (CMD38) command with argument bits se in MmcSendErase()
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H A Dmmc_core.c139 if (cntlr->curDev != NULL && cntlr->curDev->state.bits.present > 0) { in MmcCntlrSdioRescanHandle()
429 if (cntlr->caps.bits.nonremovable > 0) { in MmcCntlrDevPlugged()
464 if (cntlr->ocrDef.bits.vdd1v65To1v95 == 0) { in MmcCntlrSelectWorkVoltage()
465 ocr->bits.vdd1v65To1v95 = 0; in MmcCntlrSelectWorkVoltage()
525 if (cntlr->ops->hardwareReset != NULL && cntlr->caps.bits.hardwareReset > 0) { in MmcCntlrPowerUp()
606 if (cntlr->caps.bits.uhsSdr12 > 0 || in MmcCntlrSupportUhs()
607 cntlr->caps.bits.uhsSdr25 > 0 || in MmcCntlrSupportUhs()
608 cntlr->caps.bits.uhsSdr50 > 0 || in MmcCntlrSupportUhs()
609 cntlr->caps.bits.uhsSdr104 > 0 || in MmcCntlrSupportUhs()
610 cntlr->caps.bits in MmcCntlrSupportUhs()
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H A Dmmc_block.c44 mb->removable = (mmcDevice->state.bits.removable == 0) ? false : true; in MmcBlockInit()
H A Dmmc_sdio.c272 info->funcInfo.irqCap = cntlr->caps.bits.sdioIrq; in SdioDeviceDefaultGetCommonInfo()
397 if (cntlr->caps.bits.sdioIrq > 0) { in SdioDeviceDefaultClaimIrq()
423 if (cntlr->caps.bits.sdioIrq > 0 && cntlr->ops != NULL && cntlr->ops->setSdioIrq != NULL) { in SdioDeviceDefaultReleaseIrq()
/drivers/hdf_core/framework/model/storage/include/mmc/
H A Dmmc_caps.h75 } bits; member
94 uint32_t reserved : 18; /* bits:13~31, reserved */
95 } bits; member
H A Dmmc_corex.h223 } bits; member
254 return (mmc != NULL && mmc->state.bits.present); in MmcDeviceIsPresent()
H A Dmmc_protocol.h109 PROGRAM_CSD = 27, /* programming of the programmable bits of the CSD. */
121 * this command asks the card to send the status of the write protection bits.
203 } bits; member
206 /* SEND_STATUS rsp, card status bits */
231 * bits was made.
253 * The four bits([12:9]) are interpreted as a binary coded number between 0 and 15.
255 #define MMC_CARD_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9) /* sx, b (4 bits) */
360 * The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each,
457 #define EMMC_EXT_CSD_CARD_TYPE_MASK 0x3F /* Mask out reserved bits */
504 * The bits i
818 } bits; global() member
[all...]
/drivers/hdf_core/framework/sample/platform/uart/src/
H A Duart_pl011_sample.c11 void UartPl011SetLcrBits(struct UartRegisterMap *regMap, uint32_t bits) in UartPl011SetLcrBits() argument
16 regMap->lcr |= (bits); in UartPl011SetLcrBits()
/drivers/peripheral/codec/image/vdi/
H A Dcodec_jpeg_vdi.h54 std::vector<uint8_t> bits; member
/drivers/peripheral/codec/test/demo/jpeg/src/
H A Dcodec_jpeg_helper.cpp251 // bits in JpegDhtAssemble()
252 auto ret = memcpy_s(buffer + curPos, table[i].bits.size(), table[i].bits.data(), table[i].bits.size()); in JpegDhtAssemble()
256 HDF_LOGE("assemble bits error ret = %{public}s", buf); in JpegDhtAssemble()
259 curPos += table[i].bits.size(); in JpegDhtAssemble()
519 if (((data >> 4) & 0x0f) == 1) { // 4: low 4 bits, 1: for 16 bits in DessambleDqt()
554 table.bits.push_back(data); in DessambleDht()
/drivers/hdf_core/framework/sample/platform/uart/include/
H A Duart_pl011_sample.h50 uint32_t stopBit; /* Default stop bits */
90 /* PL011 Line Control Register Data bits */
107 #define UART_PL011_LCR_H_STP2_BIT_OFFSET 0x3u /* Two stop bits select */
208 void UartPl011SetLcrBits(struct UartRegisterMap *regMap, uint32_t bits);

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