Searched refs:set_parent (Results 1 - 5 of 5) sorted by relevance
| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-pll.c | 508 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
538 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
722 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3066_pll_set_params()
751 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
964 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3399_pll_set_params()
1000 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3399_pll_set_params()
|
| H A D | clk.c | 142 frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx); in rockchip_clk_frac_notifier_cb()
153 frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx); in rockchip_clk_frac_notifier_cb()
|
| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 185 .set_parent = vop2_mux_set_parent,
|
| /device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 203 .set_parent = vop2_mux_set_parent,
|
| /device/soc/rockchip/common/sdk_linux/include/linux/ |
| H A D | clk-provider.h | 133 * @set_parent: Change the input source of this clock; for clocks with multiple
164 * separately via calls to .set_parent and .set_rate.
234 int (*set_parent)(struct clk_hw *hw, u8 index);
member
736 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
|
Completed in 10 milliseconds