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Searched refs:rkisp_unite_set_bits (Results 1 - 14 of 14) sorted by relevance

/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Dcsi.c497 rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT, 0, RAW_RD_SIZE_ERR, true, dev->hw_dev->is_unite); in rkisp_csi_config_patch()
501 rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, true, dev->hw_dev->is_unite); in rkisp_csi_config_patch()
505 rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS, true, dev->hw_dev->is_unite); in rkisp_csi_config_patch()
H A Dcapture_v30.c304 rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite); in mp_config_mi()
320 rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite); in mp_config_mi()
393 rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite); in sp_config_mi()
410 rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite); in sp_config_mi()
437 rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, 0, CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN, in fbc_config_mi()
481 rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false, is_unite); in bp_config_mi()
497 rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false, stream->ispdev->hw_dev->is_unite); in mp_enable_mi()
502 rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, 0, CIF_MI_CTRL_SP_ENABLE, false, in sp_enable_mi()
H A Dregs.c48 rkisp_unite_set_bits(dev, stream->config->dual_crop.ctrl, mask, val, false, dev->hw_dev->is_unite); in rkisp_disable_dcrop()
141 rkisp_unite_set_bits(dev, stream->config->rsz.ctrl, 0, val, false, dev->hw_dev->is_unite); in update_rsz_shadow()
H A Dcommon.h171 static inline void rkisp_unite_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct, in rkisp_unite_set_bits() function
H A Drkisp.c507 rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK, val, false, hw->is_unite); in rkisp_trigger_read_back()
1116 rkisp_unite_set_bits(dev, CIF_ISP_CTRL, 0, CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA, in rkisp_config_color_space()
1587 rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true, dev->hw_dev->is_unite); in rkisp_config_path()
H A Dregs.h1753 rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true, is_unite); in stream_data_path()
1878 rkisp_unite_set_bits(dev, CIF_MI_CTRL, 0, val, false, is_unite); in force_cfg_update()
H A Disp_stats_v3x.c1237 rkisp_unite_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false, dev->hw_dev->is_unite); in rkisp_stats_first_ddr_config_v3x()
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/
H A Dcsi.c529 rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT, 0, RAW_RD_SIZE_ERR, in rkisp_csi_config_patch()
534 rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, in rkisp_csi_config_patch()
538 rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS, in rkisp_csi_config_patch()
H A Dcapture_v30.c321 rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite); in mp_config_mi()
339 rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite); in mp_config_mi()
413 rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite); in sp_config_mi()
432 rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite); in sp_config_mi()
459 rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, 0, in fbc_config_mi()
504 rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false, is_unite); in bp_config_mi()
519 rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, in mp_enable_mi()
525 rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, 0, in sp_enable_mi()
H A Dregs.c48 rkisp_unite_set_bits(dev, stream->config->dual_crop.ctrl, in rkisp_disable_dcrop()
152 rkisp_unite_set_bits(dev, stream->config->rsz.ctrl, 0, in update_rsz_shadow()
H A Dcommon.h183 rkisp_unite_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, in rkisp_unite_set_bits() function
H A Drkisp.c531 rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK, in rkisp_trigger_read_back()
1127 rkisp_unite_set_bits(dev, CIF_ISP_CTRL, 0, in rkisp_config_color_space()
1629 rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true, in rkisp_config_path()
H A Dregs.h1778 rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true, is_unite); in stream_data_path()
1903 rkisp_unite_set_bits(dev, CIF_MI_CTRL, 0, val, false, is_unite); in force_cfg_update()
H A Disp_stats_v3x.c1274 rkisp_unite_set_bits(dev, ISP3X_SWS_CFG, 0, in rkisp_stats_first_ddr_config_v3x()

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