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Searched refs:rk1808_pll_rates (Results 1 - 1 of 1) sorted by relevance

/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-rk1808.c32 static struct rockchip_pll_rate_table rk1808_pll_rates[] = { variable
178 PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK1808_PLL_CON(0), RK1808_MODE_CON, 0, 0, 0, rk1808_pll_rates),
181 PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK1808_PLL_CON(16), RK1808_MODE_CON, 4, 2, 0, rk1808_pll_rates),
183 PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK1808_PLL_CON(24), RK1808_MODE_CON, 6, 3, 0, rk1808_pll_rates),
185 PLL(pll_rk3036, PLL_NPLL, "npll", mux_pll_p, 0, RK1808_PLL_CON(32), RK1808_MODE_CON, 8, 5, 0, rk1808_pll_rates),
187 rk1808_pll_rates),

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