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Searched refs:rev (Results 1 - 18 of 18) sorted by relevance

/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dpcie_core.h36 #define REV_GE_64(rev) (rev >= 64)
223 uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
403 #define PCIE_IDMA_MODE_EN(rev) (REV_GE_64(rev) ? 0x1 : 0x800000) /* implicit M2M DMA mode */
459 #define PCIE_MB_TOPCIE_DB0_D2H0(rev) (REV_GE_64(rev) ? 0x0001 : 0x010000)
460 #define PCIE_MB_TOPCIE_DB0_D2H1(rev) (REV_GE_64(rev) ? 0x0002 : 0x020000)
461 #define PCIE_MB_TOPCIE_DB1_D2H0(rev) (REV_GE_6
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H A Dbcmdefs.h321 #define CHIPREV(rev) (BCMCHIPREV)
323 #define CHIPREV(rev) (rev)
327 #define PCIECOREREV(rev) (BCMPCIEREV)
329 #define PCIECOREREV(rev) (rev)
333 #define PMUREV(rev) (BCMPMUREV)
335 #define PMUREV(rev) (rev)
339 #define CCREV(rev) (BCMCCRE
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H A Dbcmutils.h1308 uint32 rev; /**< rev, e.g. core rev */ member
H A Dwlioctl.h1368 int32 rev; /**< revision specifier for ccode member
1370 * on get, rev >= 0
2223 uint32 anarev; /**< anacore rev */
2226 uint32 phyminorrev; /**< phy minor rev */
2227 uint32 coreminorrev; /**< core minor rev */
14138 WL_PROXD_METHOD_FTM = 4, /**< IEEE rev mc/2014 */
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/
H A Ddhd_custom_gpio.c248 cspec->rev = cloc_ptr->custom_locale_rev; in get_customized_country_code()
266 cspec->rev = translate_custom_table[i].custom_locale_rev; in get_customized_country_code()
273 cspec->rev = translate_custom_table[0].custom_locale_rev; in get_customized_country_code()
H A Ddhd_ccode.c262 cspec->rev = (int)simple_strtol(pch+strlen(cspec->ccode)+1, NULL, 0); in dhd_ccode_map_country_list()
269 cspec->rev = (int)simple_strtol(ccode_ww+3, NULL, 0); in dhd_ccode_map_country_list()
H A Dwldev_common.c516 cspec.rev = revinfo; in wldev_set_country()
524 WLDEV_ERROR(("%s: set country for %s as %s rev %d failed\n", in wldev_set_country()
525 __FUNCTION__, country_code, cspec.ccode, cspec.rev)); in wldev_set_country()
531 printf("%s: set country for %s as %s rev %d\n", in wldev_set_country()
532 __FUNCTION__, country_code, cspec.ccode, cspec.rev); in wldev_set_country()
H A Ddhd_config.c1559 cspec->rev = 0; in dhd_conf_map_country_list()
1564 cspec->rev = country->cspec.rev; in dhd_conf_map_country_list()
1570 cspec->rev = country->cspec.rev; in dhd_conf_map_country_list()
1578 CONFIG_MSG("%s/%d\n", cspec->ccode, cspec->rev); in dhd_conf_map_country_list()
1590 CONFIG_MSG("set country %s, revision %d\n", cspec->ccode, cspec->rev); in dhd_conf_set_country()
1595 cspec->country_abbrev, cspec->ccode, cspec->rev); in dhd_conf_set_country()
1630 cspec.rev = 0; in dhd_conf_fix_country()
2794 uint chip = 0, rev in dhd_conf_read_chiprev() local
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H A Dsiutils_priv.h80 uint32 rev; member
186 #define NOREV -1 /**< Invalid rev */
H A Daiutils.c219 SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " in ai_scan()
370 axi_wrapper[sii->axi_num_wrappers].rev = crev; in ai_scan()
375 "rev:%x, addr:%x, size:%x\n", in ai_scan()
416 axi_wrapper[sii->axi_num_wrappers].rev = crev; in ai_scan()
438 "rev:%x, addr:%x, size:%x\n", in ai_scan()
908 * or, in pcie and pci rev 13 at 8KB in ai_corereg()
1002 * or, in pcie and pci rev 13 at 8KB in ai_corereg_writeonly()
1089 * or, in pcie and pci rev 13 at 8KB in ai_corereg_addr()
1385 axi_wrapper[i].rev, in ai_dumpregs()
H A Ddhd_pcie.c1655 * for 4378B0 (rev 68). in dhdpcie_dongle_attach()
1656 * On 4378A0 (rev 66), PCIe enum reset is disabled due to CRWLPCIEGEN2-672 in dhdpcie_dongle_attach()
5610 ddo->rev = si_corerev(bus->sih); in dhdpcie_bus_doiovar()
7991 DHD_INFO(("API rev is 6, sending mb data as H2D Ctrl message to dongle, 0x%04x\n", in dhdpcie_send_mb_data()
8422 snprintf(bus_api_revision, BUS_API_REV_STR_LEN, "\nBus API revisions:(FW rev%d)(DHD rev%d)", in dhdpcie_update_bus_api_revisions()
H A Ddhd_linux.c6975 dhd->pub.dhd_cspec.rev = 0; in dhd_stop()
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_uc_fw.c100 u8 rev; /* first platform rev using this FW */ member
107 .rev = (revid_), \
117 u8 rev = INTEL_REVID(i915); in __uc_fw_auto_select() local
121 if (p == fw_blobs[i].p && rev >= fw_blobs[i].rev) { in __uc_fw_auto_select()
137 if (fw_blobs[i].p == fw_blobs[i - 1].p && fw_blobs[i].rev < fw_blobs[i - 1].rev) { in __uc_fw_auto_select()
142 fw_blobs[i - 1].rev, intel_platform_name(fw_blobs[i].p), fw_blobs[i].rev); in __uc_fw_auto_select()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/fixed/include/
H A Duart_auth.h53 hi_u8 rev[2]; /* 2: rev */ member
/device/soc/rockchip/common/sdk_linux/include/linux/usb/
H A Dpd.h90 #define PD_HEADER(type, pwr, data, rev, id, cnt, ext_hdr) \
92 ((data) == TYPEC_HOST ? PD_HEADER_DATA_ROLE : 0) | (rev << PD_HEADER_REV_SHIFT) | \
96 #define PD_HEADER_LE(type, pwr, data, rev, id, cnt) \
97 cpu_to_le16(PD_HEADER((type), (pwr), (data), (rev), (id), (cnt), (0)))
/device/soc/rockchip/common/sdk_linux/drivers/tty/serial/8250/
H A D8250_port.c930 unsigned int id1, id2, id3, rev; in autoconfig_has_efr() local
961 rev = serial_icr_read(up, UART_REV); in autoconfig_has_efr()
963 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); in autoconfig_has_efr()
969 * Enable work around for the Oxford Semiconductor 952 rev B in autoconfig_has_efr()
973 if (id3 == 0x52 && rev == 0x01) { in autoconfig_has_efr()
2660 * Oxford Semi 952 rev B workaround in serial8250_do_get_divisor()
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_drv.c437 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", base->rev, base->bytes, base->prod_id, base->ext_count); in validate_displayid()
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/
H A Ddrm_edid.c5297 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", base->rev, base->bytes, base->prod_id, base->ext_count); in validate_displayid()
6084 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", block->tag, block->rev, block->num_bytes); in drm_displayid_parse_tiled()

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