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Searched refs:reg_val (Results 1 - 25 of 43) sorted by relevance

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/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/csf/
H A Dmali_gpu_csf_registers.h255 #define GLB_VERSION_PATCH_GET(reg_val) (((reg_val)&GLB_VERSION_PATCH_MASK) >> GLB_VERSION_PATCH_SHIFT)
256 #define GLB_VERSION_PATCH_SET(reg_val, value) \
257 (((reg_val) & ~GLB_VERSION_PATCH_MASK) | (((value) << GLB_VERSION_PATCH_SHIFT) & GLB_VERSION_PATCH_MASK))
260 #define GLB_VERSION_MINOR_GET(reg_val) (((reg_val)&GLB_VERSION_MINOR_MASK) >> GLB_VERSION_MINOR_SHIFT)
261 #define GLB_VERSION_MINOR_SET(reg_val, value) \
262 (((reg_val) & ~GLB_VERSION_MINOR_MASK) | (((value) << GLB_VERSION_MINOR_SHIFT) & GLB_VERSION_MINOR_MASK))
265 #define GLB_VERSION_MAJOR_GET(reg_val) (((reg_val)
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/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/csf/
H A Dmali_gpu_csf_registers.h242 #define CS_REQ_STATE_GET(reg_val) (((reg_val)&CS_REQ_STATE_MASK) >> CS_REQ_STATE_SHIFT)
243 #define CS_REQ_STATE_SET(reg_val, value) \
244 (((reg_val) & ~CS_REQ_STATE_MASK) | (((value) << CS_REQ_STATE_SHIFT) & CS_REQ_STATE_MASK))
251 #define CS_REQ_EXTRACT_EVENT_GET(reg_val) (((reg_val)&CS_REQ_EXTRACT_EVENT_MASK) >> CS_REQ_EXTRACT_EVENT_SHIFT)
252 #define CS_REQ_EXTRACT_EVENT_SET(reg_val, value) \
253 (((reg_val) & ~CS_REQ_EXTRACT_EVENT_MASK) | (((value) << CS_REQ_EXTRACT_EVENT_SHIFT) & CS_REQ_EXTRACT_EVENT_MASK))
260 #define CS_REQ_ERROR_MODE_GET(reg_val) (((reg_val)
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/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/io/
H A Dhi_flashboot_io.c40 hi_u32 reg_val = 0; in hi_io_get_func() local
42 hi_reg_read(reg_addr, reg_val); in hi_io_get_func()
43 *val = (hi_u8)reg_val; in hi_io_get_func()
52 hi_u32 reg_val = 0; in hi_io_get_pull() local
53 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shift 2 bits */ in hi_io_get_pull()
54 *val = (hi_io_pull) ((reg_val >> IO_DRV_PULL_START_BIT) & IO_DRV_PULL_MASK); in hi_io_get_pull()
64 hi_u32 reg_val = 0; in hi_io_set_driver_strength() local
70 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shift 2 bits */ in hi_io_set_driver_strength()
71 reg_val &= ~(IO_DRV_STRENGTH_MASK << IO_DRV_STRENGTH_START_BIT); in hi_io_set_driver_strength()
72 reg_val | in hi_io_set_driver_strength()
83 hi_u32 reg_val = 0; hi_io_get_driver_strength() local
93 hi_u32 reg_val; hi_io_set_input_enable() local
106 hi_u32 reg_val; hi_io_get_input_enable() local
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/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/
H A Dmali_kbase_gpu_regmap.h284 #define AS_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \
285 (((reg_val)&AS_FAULTSTATUS_EXCEPTION_TYPE_MASK) >> AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
290 #define AS_FAULTSTATUS_ACCESS_TYPE_GET(reg_val) \
291 (((reg_val)&AS_FAULTSTATUS_ACCESS_TYPE_MASK) >> AS_FAULTSTATUS_ACCESS_TYPE_SHIFT)
300 #define AS_FAULTSTATUS_SOURCE_ID_GET(reg_val) \
301 (((reg_val)&AS_FAULTSTATUS_SOURCE_ID_MASK) >> AS_FAULTSTATUS_SOURCE_ID_SHIFT)
306 #define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_GET(reg_val) \
307 (((reg_val)&PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK) >> \
353 #define AS_LOCKADDR_LOCKADDR_SIZE_GET(reg_val) \
354 (((reg_val)
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/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/spi/
H A Dspi.c29 hi_u16 reg_val = 0; in spi_check_rx_fifo_empty() local
30 hi_reg_read16(reg_base + REG_SPI_SR, reg_val); in spi_check_rx_fifo_empty()
31 if (reg_val & MASK_SPI_SR_RNE) { in spi_check_rx_fifo_empty()
39 hi_u16 reg_val = 0; in spi_check_busy() local
40 hi_reg_read16(reg_base + REG_SPI_SR, reg_val); in spi_check_busy()
41 if (reg_val & MASK_SPI_SR_BSY) { in spi_check_busy()
49 hi_u16 reg_val = 0; in spi_check_write_timeout() local
52 hi_reg_read16(reg_base + REG_SPI_SR, reg_val); in spi_check_write_timeout()
53 if ((reg_val & MASK_SPI_SR_TFE) && (!(reg_val in spi_check_write_timeout()
68 hi_u16 reg_val = 0; spi_check_tnf_timeout() local
91 hi_u16 reg_val = 0; spi_check_rne_timeout() local
112 hi_u16 reg_val = 0; spi_flush_fifo() local
125 hi_u16 reg_val = 0; spi_disable() local
141 hi_u16 reg_val = 0; spi_enable() local
152 hi_u16 reg_val = 0; spi_reset() local
187 hi_u16 reg_val; spi_set_fifo_line() local
204 hi_u16 reg_val; spi_set_dma_fifo_line() local
278 hi_u16 reg_val = 0; spi_dma_enable() local
290 hi_u16 reg_val = 0; spi_dma_disable() local
434 hi_u16 reg_val = 0; spi_isr_enable() local
446 hi_u16 reg_val = 0; spi_isr_disable() local
456 hi_u16 reg_val = 0; spi_isr_clear_cr() local
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/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/gpio/
H A Dhi_flashboot_gpio.c38 hi_u16 reg_val = 0; in hi_gpio_get_dir() local
40 hi_reg_read16((HI_GPIO_REG_BASE + GPIO_SWPORT_DDR), reg_val); in hi_gpio_get_dir()
41 hi_io_dir_get(reg_val, (hi_u16) id, dir); in hi_gpio_get_dir()
52 hi_u16 reg_val = 0; in hi_gpio_get_output_val() local
54 hi_reg_read16((HI_GPIO_REG_BASE + GPIO_SWPORT_DR), reg_val); in hi_gpio_get_output_val()
55 hi_io_val_get(reg_val, (hi_u16) id, val); in hi_gpio_get_output_val()
66 hi_u16 reg_val = 0; in hi_gpio_set_output_val() local
68 hi_reg_read16((HI_GPIO_REG_BASE + GPIO_SWPORT_DR), reg_val); in hi_gpio_set_output_val()
69 hi_io_val_set(val, (hi_u16) id, reg_val); in hi_gpio_set_output_val()
70 hi_reg_write16((HI_GPIO_REG_BASE + GPIO_SWPORT_DR), reg_val); in hi_gpio_set_output_val()
80 hi_u16 reg_val = 0; hi_gpio_get_input_val() local
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/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/platform/vexpress/
H A Dmali_kbase_cpu_vexpress.c83 u32 reg_val = 0; in kbase_get_vexpress_cpu_clock_speed() local
115 reg_val = readl(syscfg_reg + SYS_CFGCTRL_OFFSET); in kbase_get_vexpress_cpu_clock_speed()
118 if (reg_val & SYS_CFGCTRL_START_BIT_VALUE) { in kbase_get_vexpress_cpu_clock_speed()
138 reg_val = readl(syscfg_reg + SYS_CFGSTAT_OFFSET); in kbase_get_vexpress_cpu_clock_speed()
140 if (reg_val & SYS_CFG_ERROR_BIT_VALUE) { in kbase_get_vexpress_cpu_clock_speed()
148 reg_val = readl(scc_reg); in kbase_get_vexpress_cpu_clock_speed()
157 if (IS_SINGLE_BIT_SET(reg_val, 0)) { in kbase_get_vexpress_cpu_clock_speed()
160 pa_divide = ((reg_val & (FEED_REG_BIT_MASK << in kbase_get_vexpress_cpu_clock_speed()
164 pb_divide = ((reg_val & (FEED_REG_BIT_MASK << in kbase_get_vexpress_cpu_clock_speed()
168 } else if (IS_SINGLE_BIT_SET(reg_val, in kbase_get_vexpress_cpu_clock_speed()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/pwm/
H A Dhi_pwm.c36 hi_u16 reg_val; in hi_pwm_init() local
43 hi_reg_read16(CLDO_CTL_CLKEN1_REG, reg_val); in hi_pwm_init()
47 reg_val |= 1 << CLKEN1_PWM0; in hi_pwm_init()
51 reg_val |= 1 << CLKEN1_PWM1; in hi_pwm_init()
55 reg_val |= 1 << CLKEN1_PWM2; in hi_pwm_init()
59 reg_val |= 1 << CLKEN1_PWM3; in hi_pwm_init()
63 reg_val |= 1 << CLKEN1_PWM4; in hi_pwm_init()
67 reg_val |= 1 << CLKEN1_PWM5; in hi_pwm_init()
73 reg_val |= (1 << CLKEN1_PWM_BUS) | (1 << CLKEN1_PWM); in hi_pwm_init()
74 hi_reg_write16(CLDO_CTL_CLKEN1_REG, reg_val); /* enabl in hi_pwm_init()
84 hi_u16 reg_val; pwm_deinit_clken() local
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/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/gpu/backend/
H A Dmali_kbase_gpu_regmap_csf.h208 #define GPU_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \
209 (((reg_val)&GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK) >> GPU_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
221 #define GPU_FAULTSTATUS_JASID_GET(reg_val) (((reg_val)&GPU_FAULTSTATUS_JASID_MASK) >> GPU_FAULTSTATUS_JASID_SHIFT)
222 #define GPU_FAULTSTATUS_JASID_SET(reg_val, value) \
223 (((reg_val) & ~GPU_FAULTSTATUS_JASID_MASK) | \
251 #define GPU_FAULTSTATUS_ADDRESS_VALID_GET(reg_val) \
252 (((reg_val)&GPU_FAULTSTATUS_ADDRESS_VALID_MASK) >> GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT)
253 #define GPU_FAULTSTATUS_ADDRESS_VALID_SET(reg_val, value) \
254 (((reg_val)
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/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/lsadc/
H A Dadc_drv.c22 hi_u32 reg_val = hi_reg_read_val32(REG_ADC_SR); in adc_fifo_is_empty() local
23 if (reg_val & ADC_SR_RNE) { in adc_fifo_is_empty()
46 hi_u16 reg_val; in get_ref_voltage() local
49 hi_reg_read16(LS_ADC_CLK_DIV1_REG, reg_val); in get_ref_voltage()
50 reg_val &= ~(0xF << LS_ADC_CLK_DIV1_OFFSET); in get_ref_voltage()
52 reg_val |= (0x7 << LS_ADC_CLK_DIV1_OFFSET); in get_ref_voltage()
54 reg_val |= (0xC << LS_ADC_CLK_DIV1_OFFSET); in get_ref_voltage()
56 hi_reg_write16(LS_ADC_CLK_DIV1_REG, reg_val); in get_ref_voltage()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/drivers/lsadc/
H A Dadc_drv.c22 hi_u32 reg_val = hi_reg_read_val32(REG_ADC_SR); in adc_fifo_is_empty() local
23 if (reg_val & ADC_SR_RNE) { in adc_fifo_is_empty()
46 hi_u16 reg_val; in get_ref_voltage() local
49 hi_reg_read16(LS_ADC_CLK_DIV1_REG, reg_val); in get_ref_voltage()
50 reg_val &= ~(0xF << LS_ADC_CLK_DIV1_OFFSET); in get_ref_voltage()
52 reg_val |= (0x7 << LS_ADC_CLK_DIV1_OFFSET); in get_ref_voltage()
54 reg_val |= (0xC << LS_ADC_CLK_DIV1_OFFSET); in get_ref_voltage()
56 hi_reg_write16(LS_ADC_CLK_DIV1_REG, reg_val); in get_ref_voltage()
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/boot/
H A Dlowlevel_init_v300.c87 unsigned int reg_val = 0; in trng_init() local
89 reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG104); in trng_init()
90 reg_val |= TRNG_CLK_ENABLE; in trng_init()
91 reg_set(CRG_REG_BASE + REG_PERI_CRG104, reg_val); in trng_init()
100 unsigned int reg_val = 0; in trng_deinit() local
103 reg_val = reg_get(CRG_REG_BASE + REG_PERI_CRG104); in trng_deinit()
104 reg_val &= TRNG_CLK_DISABLE; in trng_deinit()
105 reg_set(CRG_REG_BASE + REG_PERI_CRG104, reg_val); in trng_deinit()
111 unsigned int reg_val = 0; in get_random_num() local
114 reg_val in get_random_num()
141 unsigned int reg_val = 0; ddr_scramb() local
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/device/soc/rockchip/rk3588/kernel/drivers/power/supply/
H A Dcw2017_battery.c112 unsigned char reg_val = CW2017_MODE_DEFAULT; in cw2017_enable() local
114 regmap_write(cw_bat->regmap, CW2017_REG_MODE_CONFIG, reg_val); in cw2017_enable()
116 reg_val = CW2017_MODE_SLEEP; in cw2017_enable()
117 regmap_write(cw_bat->regmap, CW2017_REG_MODE_CONFIG, reg_val); in cw2017_enable()
119 reg_val = CW2017_MODE_NORMAL; in cw2017_enable()
120 regmap_write(cw_bat->regmap, CW2017_REG_MODE_CONFIG, reg_val); in cw2017_enable()
127 unsigned int reg_val = 0; in cw_update_profile() local
138 reg_val |= CW2017_CONFIG_UPDATE_FLG; in cw_update_profile()
139 reg_val &= ~CW2017_MASK_ATHD; in cw_update_profile()
140 reg_val | in cw_update_profile()
182 unsigned int reg_val; cw_init() local
279 u16 reg_val = 0; cw_get_voltage() local
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/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/i2c/
H A Di2c.c87 hi_u32 reg_val = 0; in i2c_wait() local
90 hi_reg_read32((i2c_base(id) + I2C_SR), reg_val); in i2c_wait()
91 while ((!(reg_val & I2C_INT_DONE)) && (time_out < g_i2c_ctrl[id].timeout_us)) { in i2c_wait()
94 hi_reg_read32((i2c_base(id) + I2C_SR), reg_val); in i2c_wait()
103 if (I2C_ACK_INTR & reg_val) { in i2c_wait()
107 hi_reg_read32((i2c_base(id) + I2C_ICR), reg_val); in i2c_wait()
108 hi_reg_write32((i2c_base(id) + I2C_ICR), (reg_val | I2C_CLEAR_OVER)); in i2c_wait()
115 hi_u32 reg_val = 0; in i2c_cfg_clk() local
119 hi_reg_read32((i2c_base(id) + I2C_CTRL), reg_val); in i2c_cfg_clk()
122 hi_reg_write32((i2c_base(id) + I2C_CTRL), (reg_val in i2c_cfg_clk()
136 hi_u32 reg_val = 0; i2c_start() local
172 hi_u32 reg_val = 0; i2c_stop() local
234 hi_u32 reg_val = 0; i2c_receive_byte() local
364 hi_u32 reg_val = 0; i2c_receive_last_byte() local
785 hi_u16 reg_val; hi_i2c_init() local
825 hi_u16 reg_val; hi_i2c_deinit() local
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/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/startup/
H A Dmain.c74 hi_u32 reg_val; in boot_extern_32k() local
75 hi_reg_read(HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR, reg_val); in boot_extern_32k()
76 reg_val &= ~(MSK_2_B << OFFSET_4_B); /* Maximum drive capability */ in boot_extern_32k()
77 reg_val |= (MSK_2_B << OFFSET_22_B); /* external xtal, osc enable */ in boot_extern_32k()
78 reg_val &= ~(MSK_3_B << OFFSET_25_B); in boot_extern_32k()
79 reg_val |= XTAL_DS << OFFSET_25_B; /* 1.6ua */ in boot_extern_32k()
80 reg_val &= ~(MSK_2_B << OFFSET_28_B); in boot_extern_32k()
81 reg_val |= OSC_DRV_CTL << OFFSET_28_B; /* 4Mohm */ in boot_extern_32k()
82 hi_reg_write(HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR, reg_val); in boot_extern_32k()
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/adc/
H A Dhi_adc.c26 hi_u32 reg_val = hi_reg_read_val32(REG_ADC_SR); in check_adc_fifo_empty() local
27 if (reg_val & ADC_SR_RNE) { in check_adc_fifo_empty()
56 hi_u16 reg_val, int_value; in hi_adc_read() local
64 hi_reg_read16(LS_ADC_CLK_DIV1_REG, reg_val); in hi_adc_read()
65 reg_val &= ~(0xF << LS_ADC_CLK_DIV1_OFFSET); in hi_adc_read()
67 reg_val |= (0x7 << LS_ADC_CLK_DIV1_OFFSET); in hi_adc_read()
69 reg_val |= (0xC << LS_ADC_CLK_DIV1_OFFSET); in hi_adc_read()
71 hi_reg_write16(LS_ADC_CLK_DIV1_REG, reg_val); in hi_adc_read()
/device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/
H A Dflash.h79 unsigned int reg_val = 0; in nand_io_config() local
91 reg_val = readl(MISC_REG_BASE + MISC_CTRL28); in nand_io_config()
92 reg_val &= ~0x1; in nand_io_config()
93 writel(reg_val, MISC_REG_BASE + MISC_CTRL28); in nand_io_config()
96 reg_val = readl(EMMC_PHY_INIT_CTRL); in nand_io_config()
97 reg_val |= (PHY_INIT_EN | PHY_ZCAL_EN); in nand_io_config()
98 writel(reg_val, EMMC_PHY_INIT_CTRL); in nand_io_config()
102 reg_val = readl(EMMC_PHY_INIT_CTRL); in nand_io_config()
103 if (!(reg_val & (PHY_INIT_EN | PHY_ZCAL_EN))) in nand_io_config()
H A Dnand.h36 unsigned int reg_val = readl(PERI_CRG52); in hinfc620_clk_enable() local
39 reg_val |= (PERI_CRG52_CLK_EN | PERI_CRG52_CLK_SEL_198M); in hinfc620_clk_enable()
41 reg_val &= ~PERI_CRG52_CLK_EN; in hinfc620_clk_enable()
43 writel(reg_val, (PERI_CRG52)); in hinfc620_clk_enable()
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/
H A Dflash.h79 unsigned int reg_val = 0; in nand_io_config() local
91 reg_val = readl(MISC_REG_BASE + MISC_CTRL28); in nand_io_config()
92 reg_val &= ~0x1; in nand_io_config()
93 writel(reg_val, MISC_REG_BASE + MISC_CTRL28); in nand_io_config()
96 reg_val = readl(EMMC_PHY_INIT_CTRL); in nand_io_config()
97 reg_val |= (PHY_INIT_EN | PHY_ZCAL_EN); in nand_io_config()
98 writel(reg_val, EMMC_PHY_INIT_CTRL); in nand_io_config()
102 reg_val = readl(EMMC_PHY_INIT_CTRL); in nand_io_config()
103 if (!(reg_val & (PHY_INIT_EN | PHY_ZCAL_EN))) in nand_io_config()
H A Dnand.h36 unsigned int reg_val = readl(PERI_CRG52); in hinfc620_clk_enable() local
39 reg_val |= (PERI_CRG52_CLK_EN | PERI_CRG52_CLK_SEL_198M); in hinfc620_clk_enable()
41 reg_val &= ~PERI_CRG52_CLK_EN; in hinfc620_clk_enable()
43 writel(reg_val, (PERI_CRG52)); in hinfc620_clk_enable()
/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/backend/
H A Dmali_kbase_gpu_regmap_csf.h281 #define GPU_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \
282 (((reg_val)&GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK) \
298 #define GPU_FAULTSTATUS_JASID_GET(reg_val) \
299 (((reg_val)&GPU_FAULTSTATUS_JASID_MASK) >> GPU_FAULTSTATUS_JASID_SHIFT)
300 #define GPU_FAULTSTATUS_JASID_SET(reg_val, value) \
301 (((reg_val) & ~GPU_FAULTSTATUS_JASID_MASK) | \
333 #define GPU_FAULTSTATUS_ADDRESS_VALID_GET(reg_val) \
334 (((reg_val)&GPU_FAULTSTATUS_ADDRESS_VALID_MASK) >> GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT)
335 #define GPU_FAULTSTATUS_ADDRESS_VALID_SET(reg_val, value) \
336 (((reg_val)
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/device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/src/
H A Dapp_main.c178 hi_u16 reg_val; in peripheral_close_clken() local
179 hi_reg_read16(CLDO_CTL_CLKEN_REG, reg_val); in peripheral_close_clken()
180 reg_val &= ~((1 << CLKEN_I2C0) | (1 << CLKEN_I2C1)); in peripheral_close_clken()
181 reg_val &= ~((1 << CLKEN_SPI0) | (1 << CLKEN_SPI1)); in peripheral_close_clken()
182 reg_val &= ~((1 << CLKEN_DMA_WBUS) | (1 << CLKEN_MONITOR)); in peripheral_close_clken()
183 reg_val &= ~((1 << CLKEN_TIMER1) | (1 << CLKEN_TIMER2)); in peripheral_close_clken()
184 hi_reg_write16(CLDO_CTL_CLKEN_REG, reg_val); /* disable clken0 clk gate */ in peripheral_close_clken()
187 hi_reg_read16(CLDO_CTL_CLKEN1_REG, reg_val); in peripheral_close_clken()
188 reg_val &= ~CLKEN1_PWM_ALL; in peripheral_close_clken()
189 reg_val in peripheral_close_clken()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/app/wifiiot_app/src/
H A Dapp_main.c163 hi_u16 reg_val; in peripheral_close_clken() local
164 hi_reg_read16(CLDO_CTL_CLKEN_REG, reg_val); in peripheral_close_clken()
165 reg_val &= ~((1 << CLKEN_I2C0) | (1 << CLKEN_I2C1)); in peripheral_close_clken()
166 reg_val &= ~((1 << CLKEN_SPI0) | (1 << CLKEN_SPI1)); in peripheral_close_clken()
167 reg_val &= ~((1 << CLKEN_DMA_WBUS) | (1 << CLKEN_MONITOR)); in peripheral_close_clken()
168 reg_val &= ~((1 << CLKEN_TIMER1) | (1 << CLKEN_TIMER2)); in peripheral_close_clken()
169 hi_reg_write16(CLDO_CTL_CLKEN_REG, reg_val); /* disable clken0 clk gate */ in peripheral_close_clken()
172 hi_reg_read16(CLDO_CTL_CLKEN1_REG, reg_val); in peripheral_close_clken()
173 reg_val &= ~CLKEN1_PWM_ALL; in peripheral_close_clken()
174 reg_val in peripheral_close_clken()
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/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Disp_stats_v1x.c17 u32 reg_val; in rkisp1_stats_get_awb_meas_v10() local
20 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V10); in rkisp1_stats_get_awb_meas_v10()
21 pbuf->params.awb.awb_mean[0].cnt = CIF_ISP_AWB_GET_PIXEL_CNT(reg_val); in rkisp1_stats_get_awb_meas_v10()
22 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V10); in rkisp1_stats_get_awb_meas_v10()
24 pbuf->params.awb.awb_mean[0].mean_cr_or_r = CIF_ISP_AWB_GET_MEAN_CR_R(reg_val); in rkisp1_stats_get_awb_meas_v10()
25 pbuf->params.awb.awb_mean[0].mean_cb_or_b = CIF_ISP_AWB_GET_MEAN_CB_B(reg_val); in rkisp1_stats_get_awb_meas_v10()
26 pbuf->params.awb.awb_mean[0].mean_y_or_g = CIF_ISP_AWB_GET_MEAN_Y_G(reg_val); in rkisp1_stats_get_awb_meas_v10()
32 u32 reg_val; in rkisp1_stats_get_awb_meas_v12() local
35 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V12); in rkisp1_stats_get_awb_meas_v12()
36 pbuf->params.awb.awb_mean[0].cnt = CIF_ISP_AWB_GET_PIXEL_CNT(reg_val); in rkisp1_stats_get_awb_meas_v12()
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/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/
H A Disp_stats_v1x.c19 u32 reg_val; in rkisp1_stats_get_awb_meas_v10() local
22 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V10); in rkisp1_stats_get_awb_meas_v10()
23 pbuf->params.awb.awb_mean[0].cnt = CIF_ISP_AWB_GET_PIXEL_CNT(reg_val); in rkisp1_stats_get_awb_meas_v10()
24 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V10); in rkisp1_stats_get_awb_meas_v10()
27 CIF_ISP_AWB_GET_MEAN_CR_R(reg_val); in rkisp1_stats_get_awb_meas_v10()
29 CIF_ISP_AWB_GET_MEAN_CB_B(reg_val); in rkisp1_stats_get_awb_meas_v10()
31 CIF_ISP_AWB_GET_MEAN_Y_G(reg_val); in rkisp1_stats_get_awb_meas_v10()
39 u32 reg_val; in rkisp1_stats_get_awb_meas_v12() local
42 reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V12); in rkisp1_stats_get_awb_meas_v12()
43 pbuf->params.awb.awb_mean[0].cnt = CIF_ISP_AWB_GET_PIXEL_CNT(reg_val); in rkisp1_stats_get_awb_meas_v12()
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