| /device/soc/rockchip/common/vendor/drivers/phy/ |
| H A D | phy-rockchip-naneng-edp.c | 70 struct clk *refclk;
member
247 clk_prepare_enable(edpphy->refclk);
in rockchip_edp_phy_power_on()
285 clk_disable_unprepare(edpphy->refclk);
in rockchip_edp_phy_power_off()
320 edpphy->refclk = devm_clk_get(dev, "refclk");
in rockchip_edp_phy_probe()
321 if (IS_ERR(edpphy->refclk)) {
in rockchip_edp_phy_probe()
322 ret = PTR_ERR(edpphy->refclk);
in rockchip_edp_phy_probe()
323 dev_err(dev, "failed to get refclk: %d\n", ret);
in rockchip_edp_phy_probe()
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| H A D | phy-rockchip-naneng-combphy.c | 417 struct clk *refclk = NULL;
in rk3568_combphy_cfg() local
424 if (!strncmp(priv->clks[i].id, "refclk", 0x6)) {
in rk3568_combphy_cfg()
425 refclk = priv->clks[i].clk;
in rk3568_combphy_cfg()
430 if (!refclk) {
in rk3568_combphy_cfg()
431 dev_err(priv->dev, "No refclk found\n");
in rk3568_combphy_cfg()
514 rate = clk_get_rate(refclk);
in rk3568_combphy_cfg()
566 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
in rk3568_combphy_cfg()
625 {.id = "refclk"},
641 struct clk *refclk = NULL;
in rk3588_combphy_cfg() local
648 if (!strncmp(priv->clks[i].id, "refclk", in rk3588_combphy_cfg()
[all...] |
| H A D | phy-rockchip-inno-hdmi-phy.c | 740 struct clk *refclk;
in inno_hdmi_phy_clk_register() local
744 refclk = devm_clk_get(dev, "refclk");
in inno_hdmi_phy_clk_register()
745 if (IS_ERR(refclk)) {
in inno_hdmi_phy_clk_register()
747 return PTR_ERR(refclk);
in inno_hdmi_phy_clk_register()
750 parent_name = __clk_get_name(refclk);
in inno_hdmi_phy_clk_register()
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| H A D | phy-rockchip-usbdp.c | 107 struct clk *refclk;
member
189 if (!strncmp(udphy->clks[i].id, "refclk", 0x6)) {
in udphy_clk_init()
190 udphy->refclk = udphy->clks[i].clk;
in udphy_clk_init()
195 if (!udphy->refclk) {
in udphy_clk_init()
196 dev_warn(udphy->dev, "no refclk found\n");
in udphy_clk_init()
1042 rate = clk_get_rate(udphy->refclk);
in rk3588_udphy_refclk_set()
1043 dev_dbg(udphy->dev, "refclk freq %ld\n", rate);
in rk3588_udphy_refclk_set()
1062 dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate);
in rk3588_udphy_refclk_set()
1120 /* Step 2: set init sequence and phy refclk */
in rk3588_udphy_init()
1129 dev_err(udphy->dev, "refclk se in rk3588_udphy_init()
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-naneng-edp.c | 74 struct clk *refclk; member
269 clk_prepare_enable(edpphy->refclk); in rockchip_edp_phy_power_on()
311 clk_disable_unprepare(edpphy->refclk); in rockchip_edp_phy_power_off()
344 edpphy->refclk = devm_clk_get(dev, "refclk"); in rockchip_edp_phy_probe()
345 if (IS_ERR(edpphy->refclk)) { in rockchip_edp_phy_probe()
346 ret = PTR_ERR(edpphy->refclk); in rockchip_edp_phy_probe()
347 dev_err(dev, "failed to get refclk: %d\n", ret); in rockchip_edp_phy_probe()
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| H A D | phy-rockchip-naneng-combphy.c | 422 struct clk *refclk = NULL; in rk3568_combphy_cfg() local
429 if (!strncmp(priv->clks[i].id, "refclk", 6)) { in rk3568_combphy_cfg()
430 refclk = priv->clks[i].clk; in rk3568_combphy_cfg()
435 if (!refclk) { in rk3568_combphy_cfg()
436 dev_err(priv->dev, "No refclk found\n"); in rk3568_combphy_cfg()
519 rate = clk_get_rate(refclk); in rk3568_combphy_cfg()
571 if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) { in rk3568_combphy_cfg()
630 { .id = "refclk" },
646 struct clk *refclk = NULL; in rk3588_combphy_cfg() local
653 if (!strncmp(priv->clks[i].id, "refclk", in rk3588_combphy_cfg()
[all...] |
| H A D | phy-rockchip-inno-hdmi-phy.c | 635 struct clk *refclk; in inno_hdmi_phy_clk_register() local
639 refclk = devm_clk_get(dev, "refclk"); in inno_hdmi_phy_clk_register()
640 if (IS_ERR(refclk)) { in inno_hdmi_phy_clk_register()
642 return PTR_ERR(refclk); in inno_hdmi_phy_clk_register()
645 parent_name = __clk_get_name(refclk); in inno_hdmi_phy_clk_register()
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| H A D | phy-rockchip-usbdp.c | 108 struct clk *refclk; member
257 if (!strncmp(udphy->clks[i].id, "refclk", 6)) { in udphy_clk_init()
258 udphy->refclk = udphy->clks[i].clk; in udphy_clk_init()
263 if (!udphy->refclk) in udphy_clk_init()
264 dev_warn(udphy->dev, "no refclk found\n"); in udphy_clk_init()
1081 rate = clk_get_rate(udphy->refclk); in rk3588_udphy_refclk_set()
1082 dev_dbg(udphy->dev, "refclk freq %ld\n", rate); in rk3588_udphy_refclk_set()
1099 dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate); in rk3588_udphy_refclk_set()
1158 /* Step 2: set init sequence and phy refclk */ in rk3588_udphy_init()
1168 dev_err(udphy->dev, "refclk se in rk3588_udphy_init()
[all...] |
| H A D | phy-rockchip-samsung-hdptx-hdmi.c | 1971 struct clk *refclk; in rockchip_hdptx_phy_clk_register() local
1975 refclk = devm_clk_get(dev, "ref"); in rockchip_hdptx_phy_clk_register()
1976 if (IS_ERR(refclk)) { in rockchip_hdptx_phy_clk_register()
1978 return PTR_ERR(refclk); in rockchip_hdptx_phy_clk_register()
1981 parent_name = __clk_get_name(refclk); in rockchip_hdptx_phy_clk_register()
|