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Searched refs:rank (Results 1 - 17 of 17) sorted by relevance

/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/cmd_bin/
H A Dddr_training_cmd.c172 ddrtr_res->phy_st[i].rank_st[j].item = cfg->phy[i].rank[j].item; in ddr_training_result_init()
274 unsigned int rank) in ddr_dump_wdqs_result()
286 base_phy + DDR_PHY_DXWDQSDLY(rank, i), in ddr_dump_wdqs_result()
287 ddr_read(base_phy + DDR_PHY_DXWDQSDLY(rank, i)), i); in ddr_dump_wdqs_result()
292 unsigned int rank) in ddr_dump_wdq_phase_result()
301 base_phy + DDR_PHY_DXNWDQDLY(rank, i), in ddr_dump_wdq_phase_result()
302 ddr_read(base_phy + DDR_PHY_DXNWDQDLY(rank, i)), i); in ddr_dump_wdq_phase_result()
307 unsigned int rank) in ddr_dump_wdq_bdl_result()
317 base_phy + DDR_PHY_DXNWDQNBDL0(rank, i), in ddr_dump_wdq_bdl_result()
318 ddr_read(base_phy + DDR_PHY_DXNWDQNBDL0(rank, in ddr_dump_wdq_bdl_result()
273 ddr_dump_wdqs_result(unsigned int base_phy, unsigned int byte_num, unsigned int rank) ddr_dump_wdqs_result() argument
291 ddr_dump_wdq_phase_result(unsigned int base_phy, unsigned int byte_num, unsigned int rank) ddr_dump_wdq_phase_result() argument
306 ddr_dump_wdq_bdl_result(unsigned int base_phy, unsigned int byte_num, unsigned int rank) ddr_dump_wdq_bdl_result() argument
329 ddr_dump_wdm_result(unsigned int base_phy, unsigned int byte_num, unsigned int rank) ddr_dump_wdm_result() argument
345 ddr_dump_rdqs_result(unsigned int base_phy, unsigned int byte_num, unsigned int rank) ddr_dump_rdqs_result() argument
363 ddr_dump_rdq_bdl_result(unsigned int base_phy, unsigned int byte_num, unsigned int rank) ddr_dump_rdq_bdl_result() argument
391 unsigned int rank = ddrtr_data->rank_idx; dump_result() local
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/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/
H A Dddr_phy_t12_v100.h297 #define DDR_VREF_GET_HOST_MAX(rank, val) \
299 if (0 == rank) \
306 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \
309 if (0 == rank) { \
310 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
312 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
313 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \
315 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
317 ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
318 ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_inde
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H A Dddr_phy_t12_v101.h296 #define DDR_VREF_GET_HOST_MAX(rank, val) \
298 if (0 == rank) \
305 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \
308 if (0 == rank) { \
309 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
311 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
312 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \
314 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
316 ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
317 ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_inde
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H A Dddr_phy_t28.h282 #define DDR_VREF_GET_HOST_MAX(rank, val) \
284 if (0 == rank) \
291 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \
294 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
296 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
297 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \
300 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \
302 val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
318 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \
323 base_phy + DDR_PHY_HVREFT_STATUS(rank, _
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H A Dddr_phy_s40.h260 #define DDR_VREF_GET_HOST_MAX(rank, val) \
262 if (0 == rank) \
268 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \
272 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \
287 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \
311 /* phy s40 not support rank switch */
H A Dddr_training_impl.c91 cfg->cur_item = cfg->phy[cfg->phy_idx].rank[i].item; in ddr_training_by_phy()
159 cfg->phy[0].rank[0].item = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG); in ddr_training_cfg_set_rank()
160 cfg->phy[0].rank[0].item_hw = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK0); in ddr_training_cfg_set_rank()
162 cfg->phy[0].rank[1].item = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC); in ddr_training_cfg_set_rank()
163 cfg->phy[0].rank[1].item_hw = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK1); in ddr_training_cfg_set_rank()
171 (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK0), cfg->phy[0].rank[0].item_hw, in ddr_training_cfg_set_rank()
172 (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK1), cfg->phy[0].rank[1].item_hw); in ddr_training_cfg_set_rank()
176 cfg->phy[1].rank[0].item = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG); in ddr_training_cfg_set_rank()
177 cfg->phy[1].rank[0].item_hw = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY1_RANK0); in ddr_training_cfg_set_rank()
179 cfg->phy[1].rank[ in ddr_training_cfg_set_rank()
533 unsigned int rank = cfg->rank_idx; ddr_phy_set_dq_bdl() local
564 unsigned int rank = cfg->rank_idx; ddr_phy_get_dq_bdl() local
655 unsigned int rank = cfg->rank_idx; ddr_bdl_adj() local
908 unsigned int rank = cfg->rank_idx; ddr_adjust_get_average() local
2087 unsigned int rank = cfg->rank_idx; ddr_vref_save_bdl() local
2108 unsigned int rank = cfg->rank_idx; ddr_vref_restore_bdl() local
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H A Dddr_phy_t16.h284 #define DDR_VREF_GET_HOST_MAX(rank, val) \
286 if (0 == rank) \
293 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \
305 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \
319 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \
421 /* phy t16 not support rank switch */
H A Dddr_training_impl.h232 struct ddr_bdl_st rank[DDR_RANK_NUM]; member
295 struct ddr_rank_st rank[DDR_RANK_NUM]; member
309 unsigned int rank_idx; /* current training rank index */
337 struct tr_dq_data rank[DDR_RANK_NUM]; member
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/
H A Dddr_phy_t12_v101.h297 #define DDR_VREF_GET_HOST_MAX(rank, val) \
299 if (0 == rank) \
306 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \
309 if (0 == rank) { \
310 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
312 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
313 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \
315 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
317 ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
318 ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_inde
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H A Dddr_phy_t12_v100.h298 #define DDR_VREF_GET_HOST_MAX(rank, val) \
300 if (0 == rank) \
307 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \
310 if (0 == rank) { \
311 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
313 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
314 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \
316 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
318 ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
319 ddr_write(hvreft | (val << PHY_VRFTRES_RXDIFFCAL_BIT), base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_inde
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H A Dddr_phy_t28.h283 #define DDR_VREF_GET_HOST_MAX(rank, val) \
285 if (0 == rank) \
292 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \
295 hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
297 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
298 ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \
301 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \
303 val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
319 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \
324 base_phy + DDR_PHY_HVREFT_STATUS(rank, _
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H A Dddr_phy_s40.h261 #define DDR_VREF_GET_HOST_MAX(rank, val) \
263 if (0 == rank) \
269 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \
273 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \
288 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \
312 /* phy s40 not support rank switch */
H A Dddr_training_impl.c90 cfg->cur_item = cfg->phy[cfg->phy_idx].rank[i].item; in ddr_training_by_phy()
158 cfg->phy[0].rank[0].item = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG); in ddr_training_cfg_set_rank()
159 cfg->phy[0].rank[0].item_hw = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK0); in ddr_training_cfg_set_rank()
161 cfg->phy[0].rank[1].item = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC); in ddr_training_cfg_set_rank()
162 cfg->phy[0].rank[1].item_hw = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK1); in ddr_training_cfg_set_rank()
170 (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK0), cfg->phy[0].rank[0].item_hw, in ddr_training_cfg_set_rank()
171 (DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY0_RANK1), cfg->phy[0].rank[1].item_hw); in ddr_training_cfg_set_rank()
175 cfg->phy[1].rank[0].item = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG); in ddr_training_cfg_set_rank()
176 cfg->phy[1].rank[0].item_hw = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_HW_PHY1_RANK0); in ddr_training_cfg_set_rank()
178 cfg->phy[1].rank[ in ddr_training_cfg_set_rank()
532 unsigned int rank = cfg->rank_idx; ddr_phy_set_dq_bdl() local
563 unsigned int rank = cfg->rank_idx; ddr_phy_get_dq_bdl() local
654 unsigned int rank = cfg->rank_idx; ddr_bdl_adj() local
907 unsigned int rank = cfg->rank_idx; ddr_adjust_get_average() local
2089 unsigned int rank = cfg->rank_idx; ddr_vref_save_bdl() local
2110 unsigned int rank = cfg->rank_idx; ddr_vref_restore_bdl() local
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H A Dddr_phy_t16.h285 #define DDR_VREF_GET_HOST_MAX(rank, val) \
287 if (0 == rank) \
294 #define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \
306 #define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \
320 #define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \
422 /* phy t16 not support rank switch */
H A Dddr_training_impl.h233 struct ddr_bdl_st rank[DDR_RANK_NUM]; member
296 struct ddr_rank_st rank[DDR_RANK_NUM]; member
310 unsigned int rank_idx; /* current training rank index */
338 struct tr_dq_data rank[DDR_RANK_NUM]; member
/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/lwip_sack/include/lwip/
H A Dnetif.h372 typedef err_t (*netif_set_rank_fn)(struct netif *netif, u16_t rank);
1010 err_t netif_set_rank(struct netif *netif, u16_t rank);
/device/soc/rockchip/common/vendor/drivers/devfreq/
H A Drockchip_dmc_dbg.c61 unsigned int rank; member
225 p_dram_info->ch[i].rank, p_dram_info->ch[i].buswidth, p_dram_info->ch[i].col, in dmcinfo_proc_show()

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