| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-pll.c | 66 static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll);
98 struct rockchip_clk_pll *pll; in rockchip_pll_clk_adaptive_scaling() local
104 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_adaptive_scaling()
105 if (!pll) { in rockchip_pll_clk_adaptive_scaling()
109 pll->sel = sel; in rockchip_pll_clk_adaptive_scaling()
119 struct rockchip_clk_pll *pll; in rockchip_pll_clk_rate_to_scale() local
126 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_rate_to_scale()
127 if (!pll) { in rockchip_pll_clk_rate_to_scale()
131 rate_table = pll->rate_table; in rockchip_pll_clk_rate_to_scale()
132 for (i = 0; i < pll in rockchip_pll_clk_rate_to_scale()
146 struct rockchip_clk_pll *pll; rockchip_pll_clk_scale_to_rate() local
196 rockchip_pll_clk_set_by_auto(struct rockchip_clk_pll *pll, unsigned long fin_hz, unsigned long fout_hz) rockchip_pll_clk_set_by_auto() argument
257 rockchip_rk3066_pll_clk_set_by_auto(struct rockchip_clk_pll *pll, unsigned long fin_hz, unsigned long fout_hz) rockchip_rk3066_pll_clk_set_by_auto() argument
340 rockchip_get_pll_settings(struct rockchip_clk_pll *pll, unsigned long rate) rockchip_get_pll_settings() argument
374 rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) rockchip_pll_wait_lock() argument
408 rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll) rockchip_rk3036_pll_wait_lock() argument
426 rockchip_rk3036_pll_con_to_rate(struct rockchip_clk_pll *pll, u32 con0, u32 con1) rockchip_rk3036_pll_con_to_rate() argument
444 rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, struct rockchip_pll_rate_table *rate) rockchip_rk3036_pll_get_params() argument
463 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3036_pll_recalc_rate() local
490 rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, const struct rockchip_pll_rate_table *rate) rockchip_rk3036_pll_set_params() argument
546 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3036_pll_set_rate() local
563 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3036_pll_enable() local
573 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3036_pll_disable() local
580 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3036_pll_is_enabled() local
588 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3036_pll_init() local
664 rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, struct rockchip_pll_rate_table *rate) rockchip_rk3066_pll_get_params() argument
681 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3066_pll_recalc_rate() local
705 rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, const struct rockchip_pll_rate_table *rate) rockchip_rk3066_pll_set_params() argument
759 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3066_pll_set_rate() local
790 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3066_pll_enable() local
800 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3066_pll_disable() local
807 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3066_pll_is_enabled() local
815 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3066_pll_init() local
880 rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) rockchip_rk3399_pll_wait_lock() argument
898 rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, struct rockchip_pll_rate_table *rate) rockchip_rk3399_pll_get_params() argument
919 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3399_pll_recalc_rate() local
946 rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, const struct rockchip_pll_rate_table *rate) rockchip_rk3399_pll_set_params() argument
1008 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3399_pll_set_rate() local
1033 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3399_pll_enable() local
1043 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3399_pll_disable() local
1050 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3399_pll_is_enabled() local
1058 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); rockchip_rk3399_pll_init() local
1119 struct rockchip_clk_pll *pll; rockchip_pll_clk_compensation() local
1204 struct rockchip_clk_pll *pll; rockchip_clk_register_pll() local
1339 rockchip_pll_con_to_rate(struct rockchip_clk_pll *pll, u32 con0, u32 con1) rockchip_pll_con_to_rate() argument
1358 struct rockchip_clk_pll *pll; rockchip_boost_init() local
1434 struct rockchip_clk_pll *pll; rockchip_boost_enable_recovery_sw_low() local
1455 rockchip_boost_disable_low(struct rockchip_clk_pll *pll) rockchip_boost_disable_low() argument
1466 struct rockchip_clk_pll *pll; rockchip_boost_disable_recovery_sw() local
1482 struct rockchip_clk_pll *pll; rockchip_boost_add_core_div() local
1514 struct rockchip_clk_pll *pll = (struct rockchip_clk_pll *)s->private; boost_summary_show() local
1559 struct rockchip_clk_pll *pll = (struct rockchip_clk_pll *)s->private; boost_config_show() local
1580 boost_debug_create_one(struct rockchip_clk_pll *pll, struct dentry *rootdir) boost_debug_create_one() argument
1607 struct rockchip_clk_pll *pll; boost_debug_init() local
[all...] |
| H A D | clk-rk3188.c | 698 struct rockchip_pll_clock *pll = &rk3188_pll_clks[i]; in rk3188_clk_init() local
701 if (!pll->rate_table) { in rk3188_clk_init()
705 rate = pll->rate_table; in rk3188_clk_init()
|
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/sysd/arch/hi3516cv500/hal/ |
| H A D | sys_drv.c | 240 hi_s32 pll; in sys_drv_drv_ioctrl() local
242 pll = mpp_chn->dev_id; in sys_drv_drv_ioctrl()
244 sys_hal_set_vo_pll_frac(pll, bits_set); in sys_drv_drv_ioctrl()
248 hi_s32 pll; in sys_drv_drv_ioctrl() local
250 pll = mpp_chn->dev_id; in sys_drv_drv_ioctrl()
252 sys_hal_set_vo_pll_postdiv1(pll, bits_set); in sys_drv_drv_ioctrl()
256 hi_s32 pll; in sys_drv_drv_ioctrl() local
258 pll = mpp_chn->dev_id; in sys_drv_drv_ioctrl()
260 sys_hal_set_vo_pll_postdiv2(pll, bits_set); in sys_drv_drv_ioctrl()
264 hi_s32 pll; in sys_drv_drv_ioctrl() local
272 hi_s32 pll; sys_drv_drv_ioctrl() local
[all...] |
| H A D | sys_hal.c | 277 hi_s32 sys_hal_set_vo_pll_frac(hi_s32 pll, hi_u32 bits_set) in sys_hal_set_vo_pll_frac() argument
279 if ((pll == 0) || (pll == 1)) { in sys_hal_set_vo_pll_frac()
287 hi_s32 sys_hal_set_vo_pll_postdiv1(hi_s32 pll, hi_u32 bits_set) in sys_hal_set_vo_pll_postdiv1() argument
289 if ((pll == 0) || (pll == 1)) { in sys_hal_set_vo_pll_postdiv1()
296 hi_s32 sys_hal_set_vo_pll_postdiv2(hi_s32 pll, hi_u32 bits_set) in sys_hal_set_vo_pll_postdiv2() argument
298 if ((pll == 0) || (pll == 1)) { in sys_hal_set_vo_pll_postdiv2()
305 hi_s32 sys_hal_set_vo_pll_refdiv(hi_s32 pll, hi_u3 in sys_hal_set_vo_pll_postdiv2() argument
314 sys_hal_set_vo_pll_fbdiv(hi_s32 pll, hi_u32 bits_set) sys_hal_set_vo_pll_fbdiv() argument
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-samsung-dcphy.c | 200 } pll; member
1284 S(samsung->pll.scaler) | P(samsung->pll.prediv)); in samsung_mipi_dcphy_pll_configure()
1286 if (samsung->pll.dsm < 0) { in samsung_mipi_dcphy_pll_configure()
1290 dsm_tmp = abs(samsung->pll.dsm); in samsung_mipi_dcphy_pll_configure()
1295 regmap_write(samsung->regmap, PLL_CON1, samsung->pll.dsm); in samsung_mipi_dcphy_pll_configure()
1299 M_MASK, M(samsung->pll.fbdiv)); in samsung_mipi_dcphy_pll_configure()
1301 if (samsung->pll.ssc_en) { in samsung_mipi_dcphy_pll_configure()
1303 MRR(samsung->pll.mrr) | MFR(samsung->pll in samsung_mipi_dcphy_pll_configure()
[all...] |
| /device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-inno-dsidphy.c | 247 } pll;
member
286 return container_of(hw, struct inno_dsidphy, pll.hw);
in hw_to_inno()
374 inno->pll.prediv = best_prediv;
in inno_dsidphy_pll_calc_rate()
375 inno->pll.fbdiv = best_fbdiv;
in inno_dsidphy_pll_calc_rate()
376 inno->pll.rate = best_freq;
in inno_dsidphy_pll_calc_rate()
386 unsigned int lane_mbps = inno->pll.rate / USEC_PER_SEC;
in inno_mipi_dphy_get_timing()
407 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
in inno_mipi_dphy_max_2_5GHz_pll_enable()
408 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
in inno_mipi_dphy_max_2_5GHz_pll_enable()
409 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
in inno_mipi_dphy_max_2_5GHz_pll_enable()
420 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, REG_PREDIV_MASK, REG_PREDIV(inno->pll in inno_mipi_dphy_max_1GHz_pll_enable()
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/sysd/arch/hi3516cv500/include/ |
| H A D | sys_hal.h | 98 hi_s32 sys_hal_set_vo_pll_frac(hi_s32 pll, hi_u32 bits_set);
99 hi_s32 sys_hal_set_vo_pll_postdiv1(hi_s32 pll, hi_u32 bits_set);
100 hi_s32 sys_hal_set_vo_pll_postdiv2(hi_s32 pll, hi_u32 bits_set);
101 hi_s32 sys_hal_set_vo_pll_refdiv(hi_s32 pll, hi_u32 bits_set);
102 hi_s32 sys_hal_set_vo_pll_fbdiv(hi_s32 pll, hi_u32 bits_set);
|
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/vo/vo_dev/arch/hi3516cv500/hal/ |
| H A D | vou_drv.c | 560 hi_s32 vo_drv_check_dev_pll_param(hi_vo_dev dev, hi_vo_user_intfsync_pll *pll) in vo_drv_check_dev_pll_param() argument
562 if ((pll->fbdiv > VO_PLL_FBDIV_MAX) || in vo_drv_check_dev_pll_param()
563 (pll->frac > VO_PLL_FRAC_MAX) || in vo_drv_check_dev_pll_param()
564 (pll->refdiv > VO_PLL_REFDIV_MAX) || in vo_drv_check_dev_pll_param()
565 (pll->refdiv == 0) || in vo_drv_check_dev_pll_param()
566 (pll->postdiv1 > VO_PLL_POSTDIV1_MAX) || in vo_drv_check_dev_pll_param()
567 (pll->postdiv1 == 0) || in vo_drv_check_dev_pll_param()
568 (pll->postdiv2 > VO_PLL_POSTDIV2_MAX) || in vo_drv_check_dev_pll_param()
569 (pll->postdiv2 == 0)) { in vo_drv_check_dev_pll_param()
570 vo_err_trace("dev(%d) pll para in vo_drv_check_dev_pll_param()
579 vo_drv_check_dev_pll_postdiv(hi_vo_dev dev, hi_vo_user_intfsync_pll *pll) vo_drv_check_dev_pll_postdiv() argument
591 vo_drv_check_dev_pll_foutvco(hi_vo_dev dev, hi_vo_user_intfsync_pll *pll) vo_drv_check_dev_pll_foutvco() argument
607 vo_drv_check_dev_pll(hi_vo_dev dev, hi_vo_user_intfsync_pll *pll) vo_drv_check_dev_pll() argument
[all...] |
| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_drm_vop.c | 277 struct rockchip_dclk_pll *pll; member
2325 if (clk_is_match(private->default_pll.pll, parent)) { in vop_crtc_loader_protect()
2326 vop->pll = &private->default_pll; in vop_crtc_loader_protect()
2327 } else if (clk_is_match(private->hdmi_pll.pll, parent)) { in vop_crtc_loader_protect()
2328 vop->pll = &private->hdmi_pll; in vop_crtc_loader_protect()
2330 if (vop->pll) { in vop_crtc_loader_protect()
2331 vop->pll->use_count++; in vop_crtc_loader_protect()
2343 if (vop->dclk_source && vop->pll) { in vop_crtc_loader_protect()
2344 vop->pll->use_count--; in vop_crtc_loader_protect()
2345 vop->pll in vop_crtc_loader_protect()
[all...] |
| H A D | rockchip_drm_drv.c | 1253 private->hdmi_pll.pll = devm_clk_get_optional(dev, "hdmi-tmds-pll"); in rockchip_drm_bind()
1254 if (PTR_ERR(private->hdmi_pll.pll) == -EPROBE_DEFER) { in rockchip_drm_bind()
1257 } else if (IS_ERR(private->hdmi_pll.pll)) { in rockchip_drm_bind()
1258 dev_err(dev, "failed to get hdmi-tmds-pll\n"); in rockchip_drm_bind()
1259 ret = PTR_ERR(private->hdmi_pll.pll); in rockchip_drm_bind()
1262 private->default_pll.pll = devm_clk_get_optional(dev, "default-vop-pll"); in rockchip_drm_bind()
1263 if (PTR_ERR(private->default_pll.pll) == -EPROBE_DEFER) { in rockchip_drm_bind()
1266 } else if (IS_ERR(private->default_pll.pll)) { in rockchip_drm_bind()
[all...] |
| H A D | rockchip_drm_drv.h | 330 struct clk *pll; member
|
| /device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/ |
| H A D | start.S | 147 mov r3, #0x2 @ full reset pll + mpu
|
| /device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/boot/ |
| H A D | start.S | 147 mov r3, #0x2 @ full reset pll + mpu
|
| /device/soc/rockchip/rk3588/kernel/drivers/devfreq/ |
| H A D | rockchip_drm_drv.h | 337 struct clk *pll; member
|