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Searched refs:phy_cfg (Results 1 - 15 of 15) sorted by relevance

/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-inno-hdmi-phy.c171 struct phy_config *phy_cfg; member
212 int (*power_on)(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg, const struct phy_config *phy_cfg);
538 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; in inno_hdmi_phy_power_on() local
542 if (inno->phy_cfg) { in inno_hdmi_phy_power_on()
543 phy_cfg = inno->phy_cfg; in inno_hdmi_phy_power_on()
563 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) { in inno_hdmi_phy_power_on()
564 if (tmdsclock <= phy_cfg->tmdsclock) { in inno_hdmi_phy_power_on()
569 if (cfg->tmdsclock == ~0UL || phy_cfg in inno_hdmi_phy_power_on()
779 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg, const struct phy_config *phy_cfg) inno_hdmi_phy_rk3228_power_on() argument
952 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg, const struct phy_config *phy_cfg) inno_hdmi_phy_rk3328_power_on() argument
1247 inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config, struct phy_config *phy_cfg, int phy_table_size) inno_hdmi_update_phy_table() argument
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H A Dphy-rockchip-naneng-combphy.c295 const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; in rockchip_combphy_parse_dt() local
320 param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en, false); in rockchip_combphy_parse_dt()
322 param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en, false); in rockchip_combphy_parse_dt()
326 param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, true); in rockchip_combphy_parse_dt()
361 const struct rockchip_combphy_cfg *phy_cfg; in rockchip_combphy_probe() local
365 phy_cfg = of_device_get_match_data(dev); in rockchip_combphy_probe()
366 if (!phy_cfg) { in rockchip_combphy_probe()
383 priv->num_clks = phy_cfg->num_clks; in rockchip_combphy_probe()
385 priv->clks = devm_kmemdup(dev, phy_cfg->clks, phy_cfg in rockchip_combphy_probe()
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/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi-phy.c174 struct phy_config *phy_cfg; member
217 const struct phy_config *phy_cfg);
447 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table; in inno_hdmi_phy_power_on() local
451 if (inno->phy_cfg) in inno_hdmi_phy_power_on()
452 phy_cfg = inno->phy_cfg; in inno_hdmi_phy_power_on()
471 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++) in inno_hdmi_phy_power_on()
472 if (tmdsclock <= phy_cfg->tmdsclock) in inno_hdmi_phy_power_on()
475 if (cfg->tmdsclock == ~0UL || phy_cfg in inno_hdmi_phy_power_on()
675 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg, const struct phy_config *phy_cfg) inno_hdmi_phy_rk3228_power_on() argument
857 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, const struct post_pll_config *cfg, const struct phy_config *phy_cfg) inno_hdmi_phy_rk3328_power_on() argument
1162 inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config, struct phy_config *phy_cfg, int phy_table_size) inno_hdmi_update_phy_table() argument
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H A Dphy-rockchip-naneng-combphy.c298 const struct rockchip_combphy_cfg *phy_cfg = priv->cfg; in rockchip_combphy_parse_dt() local
323 param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en, in rockchip_combphy_parse_dt()
326 param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en, in rockchip_combphy_parse_dt()
331 param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel, in rockchip_combphy_parse_dt()
367 const struct rockchip_combphy_cfg *phy_cfg; in rockchip_combphy_probe() local
371 phy_cfg = of_device_get_match_data(dev); in rockchip_combphy_probe()
372 if (!phy_cfg) { in rockchip_combphy_probe()
388 priv->num_clks = phy_cfg->num_clks; in rockchip_combphy_probe()
390 priv->clks = devm_kmemdup(dev, phy_cfg->clks, in rockchip_combphy_probe()
391 phy_cfg in rockchip_combphy_probe()
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H A Dphy-rockchip-samsung-hdptx-hdmi.c707 struct phy_config *phy_cfg; member
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/
H A Ddrv_hdmi_frl.c156 hdmi_phy_cfg phy_cfg = {0}; in frl_tx_ffe_set() local
158 phy_cfg.mode_cfg = HDMI_PHY_MODE_CFG_TXFFE; in frl_tx_ffe_set()
159 phy_cfg.rate = (hdmi_work_mode)hdmi_dev->frl_info.rate_info.cur_rate; in frl_tx_ffe_set()
162 hal_call_void(hal_hdmi_phy_set, hdmi_dev->hal, &phy_cfg); in frl_tx_ffe_set()
170 hdmi_phy_cfg phy_cfg = {0}; in frl_phy_set() local
178 phy_cfg.emi_enable = hdmi_dev->emi_enable; in frl_phy_set()
179 phy_cfg.pixel_clk = vo_attr->clk_fs; in frl_phy_set()
180 phy_cfg.tmds_clk = vo_attr->hdmi_adapt_pix_clk; in frl_phy_set()
181 phy_cfg.deep_color = app_attr->deep_color_mode; in frl_phy_set()
182 phy_cfg in frl_phy_set()
498 hdmi_phy_cfg phy_cfg = {0}; frl_train_exception() local
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H A Ddrv_hdmi_debug.c2839 hdmi_phy_cfg phy_cfg = {0}; in debug_frl_ffe() local
2849 phy_cfg.aen_tx_ffe[0] = data; in debug_frl_ffe()
2853 phy_cfg.aen_tx_ffe[1] = data; in debug_frl_ffe()
2857 phy_cfg.aen_tx_ffe[2] = data; in debug_frl_ffe()
2861 phy_cfg.aen_tx_ffe[3] = data; in debug_frl_ffe()
2863 if (phy_cfg.aen_tx_ffe[0] > FRL_TXFFE_MODE_3 || in debug_frl_ffe()
2864 phy_cfg.aen_tx_ffe[1] > FRL_TXFFE_MODE_3 || in debug_frl_ffe()
2865 phy_cfg.aen_tx_ffe[2] > FRL_TXFFE_MODE_3 || in debug_frl_ffe()
2866 phy_cfg.aen_tx_ffe[3] > FRL_TXFFE_MODE_3) { in debug_frl_ffe()
2871 phy_cfg in debug_frl_ffe()
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H A Ddrv_hdmi_intf.c2046 hdmi_phy_cfg phy_cfg = {0}; local
2053 phy_cfg.pixel_clk =
2055 phy_cfg.emi_enable = hdmi_dev->emi_enable;
2056 phy_cfg.tmds_clk = vo_attr->hdmi_adapt_pix_clk;
2057 phy_cfg.deep_color = app_attr->deep_color_mode;
2058 phy_cfg.trace_len = hdmi_dev->mode_param.trace_len;
2060 phy_cfg.color_space = app_attr->out_color_space;
2062 phy_cfg.mode_cfg = HDMI_PHY_MODE_CFG_FRL;
2063 (hi_void)memset_s(phy_cfg.aen_tx_ffe, sizeof(phy_cfg
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/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.c580 union phy_configure_opts phy_cfg = {0}; in analogix_dp_set_link_bandwidth() local
582 phy_cfg.dp.lanes = dp->link_train.lane_count; in analogix_dp_set_link_bandwidth()
583 phy_cfg.dp.link_rate = drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; in analogix_dp_set_link_bandwidth()
584 phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp); in analogix_dp_set_link_bandwidth()
585 phy_cfg.dp.set_lanes = false; in analogix_dp_set_link_bandwidth()
586 phy_cfg.dp.set_rate = true; in analogix_dp_set_link_bandwidth()
587 phy_cfg.dp.set_voltages = false; in analogix_dp_set_link_bandwidth()
588 ret = phy_configure(dp->phy, &phy_cfg); in analogix_dp_set_link_bandwidth()
626 union phy_configure_opts phy_cfg = {0}; in analogix_dp_set_lane_count() local
628 phy_cfg in analogix_dp_set_lane_count()
658 union phy_configure_opts phy_cfg = {0}; analogix_dp_set_lane_link_training() local
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/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-usb2.c295 * @phy_cfg: phy register configuration, assigned by driver data.
315 const struct rockchip_usb2phy_cfg *phy_cfg; member
378 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) { in rockchip_usb2phy_clk480m_prepare()
379 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true); in rockchip_usb2phy_clk480m_prepare()
397 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); in rockchip_usb2phy_clk480m_unprepare()
405 return property_enabled(base, &rphy->phy_cfg->clkout_ctl); in rockchip_usb2phy_clk480m_prepared()
919 if (rphy->phy_cfg->vbus_detect) { in rockchip_usb2phy_set_mode()
920 rphy->phy_cfg->vbus_detect(rphy, vbus_det_en); in rockchip_usb2phy_set_mode()
944 for (index = 0; index < rphy->phy_cfg->num_ports; index++) { in otg_mode_show()
982 for (index = 0; index < rphy->phy_cfg in otg_mode_store()
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H A Dphy-rockchip-typec.c677 const struct phy_reg *phy_cfg; in tcphy_cfg_dp_pll() local
688 phy_cfg = dp_pll_hbr2_cfg; in tcphy_cfg_dp_pll()
694 phy_cfg = dp_pll_hbr_cfg; in tcphy_cfg_dp_pll()
701 phy_cfg = dp_pll_rbr_cfg; in tcphy_cfg_dp_pll()
712 writel(phy_cfg[i].value, tcphy->base + phy_cfg[i].addr); in tcphy_cfg_dp_pll()
845 const struct phy_reg *phy_cfg; in tcphy_dp_set_link_rate() local
898 phy_cfg = ssc_on ? dp_pll_rbr_ssc_cfg : dp_pll_rbr_cfg; in tcphy_dp_set_link_rate()
905 phy_cfg = ssc_on ? dp_pll_hbr_ssc_cfg : dp_pll_hbr_cfg; in tcphy_dp_set_link_rate()
912 phy_cfg in tcphy_dp_set_link_rate()
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/ctrl/hisiv100/
H A Dhdmi_hal_intf.c327 static hi_void hal_hdmi_phy_set(const struct hdmi_hal_ *hal, hdmi_phy_cfg *phy_cfg) in hal_hdmi_phy_set() argument
332 hdmi_if_null_return_void(phy_cfg); in hal_hdmi_phy_set()
334 cfg.deep_color = phy_cfg->deep_color; in hal_hdmi_phy_set()
335 cfg.emi_enable = phy_cfg->emi_enable; in hal_hdmi_phy_set()
336 cfg.mode_cfg = phy_cfg->mode_cfg; in hal_hdmi_phy_set()
337 cfg.pixel_clk = phy_cfg->pixel_clk; in hal_hdmi_phy_set()
338 cfg.tmds_clk = phy_cfg->tmds_clk; in hal_hdmi_phy_set()
339 cfg.trace_len = phy_cfg->trace_len; in hal_hdmi_phy_set()
343 hi_unused(phy_cfg); in hal_hdmi_phy_set()
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Ddw-dp.c639 union phy_configure_opts phy_cfg; in dw_dp_link_train_update_vs_emph() local
648 phy_cfg.dp.voltage[i] = vs[i]; in dw_dp_link_train_update_vs_emph()
649 phy_cfg.dp.pre[i] = pe[i]; in dw_dp_link_train_update_vs_emph()
651 phy_cfg.dp.lanes = lanes; in dw_dp_link_train_update_vs_emph()
652 phy_cfg.dp.link_rate = link->rate / 0x64; in dw_dp_link_train_update_vs_emph()
653 phy_cfg.dp.set_lanes = false; in dw_dp_link_train_update_vs_emph()
654 phy_cfg.dp.set_rate = false; in dw_dp_link_train_update_vs_emph()
655 phy_cfg.dp.set_voltages = true; in dw_dp_link_train_update_vs_emph()
656 ret = phy_configure(dp->phy, &phy_cfg); in dw_dp_link_train_update_vs_emph()
675 union phy_configure_opts phy_cfg; in dw_dp_link_configure() local
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/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
H A Ddw-dp.c654 union phy_configure_opts phy_cfg; in dw_dp_link_train_update_vs_emph() local
663 phy_cfg.dp.voltage[i] = vs[i]; in dw_dp_link_train_update_vs_emph()
664 phy_cfg.dp.pre[i] = pe[i]; in dw_dp_link_train_update_vs_emph()
666 phy_cfg.dp.lanes = lanes; in dw_dp_link_train_update_vs_emph()
667 phy_cfg.dp.link_rate = link->rate / 100; in dw_dp_link_train_update_vs_emph()
668 phy_cfg.dp.set_lanes = false; in dw_dp_link_train_update_vs_emph()
669 phy_cfg.dp.set_rate = false; in dw_dp_link_train_update_vs_emph()
670 phy_cfg.dp.set_voltages = true; in dw_dp_link_train_update_vs_emph()
671 ret = phy_configure(dp->phy, &phy_cfg); in dw_dp_link_train_update_vs_emph()
688 union phy_configure_opts phy_cfg; in dw_dp_link_configure() local
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/hal/
H A Dhdmi_hal.h88 hi_void (*hal_hdmi_phy_set)(const struct hdmi_hal_ *hal, hdmi_phy_cfg *phy_cfg);

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