| /device/soc/hisilicon/common/platform/mmc/sdhci/ |
| H A D | sdhci.c | 668 static void SdhciSetDrvPhase(uint32_t id, uint32_t phase) in SdhciSetDrvPhase() argument
679 value |= (phase << SDHCI_DRV_CLK_PHASE_SHFT); in SdhciSetDrvPhase()
692 static void SdhciSetSampPhase(struct SdhciHost *host, uint32_t phase) in SdhciSetSampPhase() argument
698 val |= phase; in SdhciSetSampPhase()
840 uint32_t drvPhase, phase; in SdhciSetPhase() local
852 phase = host->tuningPhase; in SdhciSetPhase()
855 phase = host->tuningPhase; in SdhciSetPhase()
858 phase = SDHCI_SAMPLE_PHASE; in SdhciSetPhase()
861 phase = SDHCI_SAMPLE_PHASE; in SdhciSetPhase()
864 phase in SdhciSetPhase()
1360 SdhciSelectSamplPhase(struct SdhciHost *host, uint32_t phase) SdhciSelectSamplPhase() argument
1399 uint32_t phase, fall, rise, fallUpdateFlag, index; SdhciDoTune() local
[all...] |
| H A D | sdhci.h | 147 * [4:0]Clock phase configuration for B clock debugging during edge detection. The default value is 90 degrees.
152 #define SDHCI_SAMPLB_SEL(phase) ((phase) << 0)
156 * [28:24]Clock phase configuration. Default value: 180.
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| /device/soc/rockchip/common/sdk_linux/drivers/mmc/host/ |
| H A D | dw_mmc-rockchip.c | 89 * Set the drive phase offset based on speed mode to achieve hold times.
in dw_mci_rk3288_set_ios()
115 int phase;
in dw_mci_rk3288_set_ios() local
118 * In almost all cases a 90 degree phase offset will provide
in dw_mci_rk3288_set_ios()
123 phase = RK_NINTY_DEGREE_PHASE;
in dw_mci_rk3288_set_ios()
129 * bus width is 8 we need to double the phase offset
in dw_mci_rk3288_set_ios()
133 phase = RK_ONE_HUNDRED_EIGHTY_DEGREE_PHASE;
in dw_mci_rk3288_set_ios()
146 phase = RK_ONE_HUNDRED_EIGHTY_DEGREE_PHASE;
in dw_mci_rk3288_set_ios()
150 clk_set_phase(priv->drv_clk, phase);
in dw_mci_rk3288_set_ios()
190 dev_info(host->dev, "Successfully tuned phase to %d\n", degrees[i]);
in dw_mci_v2_execute_tuning()
231 /* Try each phase an in dw_mci_rk3288_execute_tuning()
[all...] |
| /device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/ |
| H A D | ddr_training_impl.c | 1042 /* clear wdq phase */ in ddr_adjust_set_val()
1062 /* decrease wdq phase, window move to right */ in ddr_adjust_change_val()
2410 /* DDR PHY DQ phase increase */
2427 /* DDR PHY DQ phase decrease */
2526 /* adjust wdq phase, wdq bdl, wdm bdl */ in ddr_wl_wdq_adjust()
2528 if (wdqs_new->phase[i] == wdqs_old->phase[i] in ddr_wl_wdq_adjust()
2572 DDR_INFO("Byte[%x] WDQ adjust phase[%x] bdl[%x]", in ddr_wl_wdq_adjust()
2584 /* Sync WDQ phase, WDQ bdl, WDM bdl, OEN bdl, WDQ SOE bdl by WDQS value */
2598 /* sync wdq phase, wd in ddr_wl_bdl_sync()
3580 unsigned int phase; ddr_lpca_loop_phase() local
3643 unsigned int phase; ddr_lpca_adjust() local
[all...] |
| H A D | ddr_training_impl.h | 236 unsigned int phase[DDR_PHY_BYTE_MAX]; member
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| /device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/ |
| H A D | ddr_training_impl.c | 1041 /* clear wdq phase */ in ddr_adjust_set_val()
1061 /* decrease wdq phase, window move to right */ in ddr_adjust_change_val()
2412 /* DDR PHY DQ phase increase */
2429 /* DDR PHY DQ phase decrease */
2528 /* adjust wdq phase, wdq bdl, wdm bdl */ in ddr_wl_wdq_adjust()
2530 if (wdqs_new->phase[i] == wdqs_old->phase[i] in ddr_wl_wdq_adjust()
2574 DDR_INFO("Byte[%x] WDQ adjust phase[%x] bdl[%x]", in ddr_wl_wdq_adjust()
2586 /* Sync WDQ phase, WDQ bdl, WDM bdl, OEN bdl, WDQ SOE bdl by WDQS value */
2600 /* sync wdq phase, wd in ddr_wl_bdl_sync()
3582 unsigned int phase; ddr_lpca_loop_phase() local
3645 unsigned int phase; ddr_lpca_adjust() local
[all...] |
| H A D | ddr_training_impl.h | 237 unsigned int phase[DDR_PHY_BYTE_MAX]; member
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| /device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/ |
| H A D | mmc.h | 85 #define SDIO_SAMPLB_SEL(phase) ((phase) << 0)
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| /device/soc/hisilicon/common/platform/mmc/himci_v200/ |
| H A D | himci.c | 982 uint32_t phase; in HimciCfgPhase() local
987 phase = DRV_PHASE_135 | SMP_PHASE_0; in HimciCfgPhase()
989 phase = DRV_PHASE_180 | SMP_PHASE_45; in HimciCfgPhase()
991 phase = DRV_PHASE_180 | SMP_PHASE_0; in HimciCfgPhase()
995 phase = DRV_PHASE_135 | SMP_PHASE_0; in HimciCfgPhase()
997 phase = DRV_PHASE_90 | SMP_PHASE_0; in HimciCfgPhase()
999 phase = DRV_PHASE_180 | SMP_PHASE_45; in HimciCfgPhase()
1001 phase = DRV_PHASE_135 | SMP_PHASE_45; in HimciCfgPhase()
1003 phase = DRV_PHASE_180 | SMP_PHASE_0; in HimciCfgPhase()
1009 value |= phase; in HimciCfgPhase()
1213 HimciSetSapPhase(struct HimciHost *host, uint32_t phase) HimciSetSapPhase() argument
[all...] |
| /device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/ |
| H A D | bcmmsgbuf.h | 627 uint32 phase :1; /* Phase bit */
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| H A D | bcmevent.h | 687 uint8 phase; member
|