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Searched refs:parent_names (Results 1 - 21 of 21) sorted by relevance

/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk.c37 static struct clk *rockchip_clk_register_branch(const char *name, const char *const *parent_names, u8 num_parents, in rockchip_clk_register_branch() argument
100 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux ? &mux->hw : NULL, mux_ops, in rockchip_clk_register_branch()
222 const char *const *parent_names, u8 num_parents, in rockchip_clk_register_frac_branch()
271 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, NULL, NULL, &div->hw, div_ops, in rockchip_clk_register_frac_branch()
284 frac->mux_frac_idx = match_string(child->parent_names, child->num_parents, name); in rockchip_clk_register_frac_branch()
301 init.parent_names = child->parent_names; in rockchip_clk_register_frac_branch()
327 static struct clk *rockchip_clk_register_factor_branch(const char *name, const char *const *parent_names, in rockchip_clk_register_factor_branch() argument
338 return clk_register_fixed_factor(NULL, name, parent_names[0], flags, mult, div); in rockchip_clk_register_factor_branch()
360 hw = clk_hw_register_composite(NULL, name, parent_names, num_parent in rockchip_clk_register_factor_branch()
221 rockchip_clk_register_frac_branch(struct rockchip_clk_provider *ctx, const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, struct rockchip_clk_branch *child, unsigned long max_prate, spinlock_t *lock) rockchip_clk_register_frac_branch() argument
371 rockchip_clk_register_composite_brother_branch( struct rockchip_clk_provider *ctx, const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u32 *mux_table, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, struct rockchip_clk_branch *brother, spinlock_t *lock) rockchip_clk_register_composite_brother_branch() argument
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H A Dclk.h348 * @parent_names: name of the parent clock.
366 const char *const *parent_names; member
382 .id = (_id), .type = (_type), .name = (_name), .parent_names = (_pnames), .num_parents = ARRAY_SIZE(_pnames), \
388 const char *name, const char *const *parent_names, u8 num_parents, int con_offset,
440 struct clk *rockchip_clk_register_mmc(const char *name, const char *const *parent_names, u8 num_parents,
455 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, const char *const *parent_names, u8 num_parents,
461 struct clk *rockchip_clk_register_inverter(const char *name, const char *const *parent_names, u8 num_parents,
464 struct clk *rockchip_clk_register_muxgrf(const char *name, const char *const *parent_names, u8 num_parents, int flags,
490 const char *const *parent_names; member
512 .id = (_id), .branch_type = branch_composite, .name = (cname), .parent_names
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H A Dclk-ddr.c218 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, const char *const *parent_names, u8 num_parents, in rockchip_clk_register_ddrclk() argument
238 init.parent_names = parent_names; in rockchip_clk_register_ddrclk()
H A Dclk-half-divider.c148 struct clk *rockchip_clk_register_halfdiv(const char *name, const char *const *parent_names, u8 num_parents, in rockchip_clk_register_halfdiv() argument
205 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux ? &mux->hw : NULL, mux_ops, in rockchip_clk_register_halfdiv()
H A Dclk-pll.c1198 const char *name, const char *const *parent_names, u8 num_parents, int con_offset, in rockchip_clk_register_pll()
1242 pll_parents[0x0] = parent_names[0x0]; in rockchip_clk_register_pll()
1244 pll_parents[0x2] = parent_names[0x1]; in rockchip_clk_register_pll()
1249 init.parent_names = pll_parents; in rockchip_clk_register_pll()
1271 init.parent_names = &parent_names[0]; in rockchip_clk_register_pll()
1197 rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, enum rockchip_pll_type pll_type, const char *name, const char *const *parent_names, u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, unsigned long flags, u8 clk_pll_flags) rockchip_clk_register_pll() argument
H A Dclk-cpu.c273 init.parent_names = &parent_name; in rockchip_clk_register_cpuclk()
/device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/
H A Dclk.h417 * @parent_names: name of the parent clock.
435 const char *const *parent_names; member
455 .parent_names = _pnames, \
468 const char *name, const char *const *parent_names,
529 const char *const *parent_names, u8 num_parents,
545 const char *const *parent_names,
554 const char *const *parent_names, u8 num_parents,
559 const char *const *parent_names, u8 num_parents,
586 const char *const *parent_names; member
612 .parent_names
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/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk.h417 * @parent_names: name of the parent clock.
435 const char *const *parent_names; member
455 .parent_names = _pnames, \
468 const char *name, const char *const *parent_names,
529 const char *const *parent_names, u8 num_parents,
545 const char *const *parent_names,
554 const char *const *parent_names, u8 num_parents,
559 const char *const *parent_names, u8 num_parents,
586 const char *const *parent_names; member
612 .parent_names
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H A Dclk-dclk-divider.c92 const char *const *parent_names, in rockchip_clk_register_dclk_branch()
156 clk = clk_register_composite(NULL, name, parent_names, num_parents, in rockchip_clk_register_dclk_branch()
91 rockchip_clk_register_dclk_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, unsigned long max_prate, spinlock_t *lock) rockchip_clk_register_dclk_branch() argument
H A Dclk-link.c60 init.parent_names = &priv->pname; in register_clocks()
H A Dclk-pvtm.c175 init.parent_names = NULL; in clock_pvtm_regitstor()
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c36 .branch_type = branch_mux, .name = (cname), .parent_names = (pnames), .num_parents = ARRAY_SIZE(pnames), \
42 .branch_type = branch_factor, .name = (cname), .parent_names = (const char *[128]) {pname}, \
48 .branch_type = branch_divider, .name = (cname), .parent_names = (const char *[128]) {pname}, \
55 const char *const *parent_names; member
281 init.parent_names = branch->parent_names; in vop2_clk_register()
287 init.parent_names = NULL; in vop2_clk_register()
/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c39 .parent_names = pnames, \
48 .parent_names = (const char *[]){ pname }, \
57 .parent_names = (const char *[]){ pname }, \
66 const char *const *parent_names; member
297 init.parent_names = branch->parent_names; in vop2_clk_register()
303 init.parent_names = NULL; in vop2_clk_register()
/device/soc/rockchip/common/sdk_linux/include/linux/
H A Dclk-provider.h135 * as a u8 corresponding to the parent in either the .parent_names
143 * .parent_names or .parents arrays. In short, this function
268 * @parent_names: array of string names for all possible parents
280 const char *const *parent_names; member
777 const char *const *parent_names, const struct clk_hw **parent_hws,
780 struct clk *clk_register_mux_table(struct device *dev, const char *name, const char *const *parent_names,
784 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, shift, width, clk_mux_flags, lock) \
785 clk_register_mux_table((dev), (name), (parent_names), (num_parents), (flags), (reg), (shift), BIT((width)) - 1, \
787 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, flags, reg, shift, mask, clk_mux_flags, table, \
789 __clk_hw_register_mux((dev), NULL, (name), (num_parents), (parent_names), NUL
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/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-dclk-divider.c92 struct clk *rockchip_clk_register_dclk_branch(const char *name, const char *const *parent_names, u8 num_parents, in rockchip_clk_register_dclk_branch() argument
151 clk = clk_register_composite(NULL, name, parent_names, num_parents, mux ? &mux->hw : NULL, mux_ops, in rockchip_clk_register_dclk_branch()
H A Dclk-pvtm.c173 init.parent_names = NULL; in clock_pvtm_regitstor()
/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c793 init.parent_names = &clk_name; in rockchip_usb_phy_init()
797 init.parent_names = NULL; in rockchip_usb_phy_init()
H A Dphy-rockchip-inno-usb2.c444 init.parent_names = &clk_name; in rockchip_usb2phy_clk480m_register()
447 init.parent_names = NULL; in rockchip_usb2phy_clk480m_register()
/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-inno-hdmi-phy.c752 init.parent_names = &parent_name; in inno_hdmi_phy_clk_register()
/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi-phy.c647 init.parent_names = &parent_name; in inno_hdmi_phy_clk_register()
H A Dphy-rockchip-samsung-hdptx-hdmi.c1983 init.parent_names = &parent_name; in rockchip_hdptx_phy_clk_register()

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