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Searched refs:num_parents (Results 1 - 21 of 21) sorted by relevance

/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk.h349 * @num_parents: number of parents
367 u8 num_parents; member
382 .id = (_id), .type = (_type), .name = (_name), .parent_names = (_pnames), .num_parents = ARRAY_SIZE(_pnames), \
388 const char *name, const char *const *parent_names, u8 num_parents, int con_offset,
435 struct clk *rockchip_clk_register_cpuclk(const char *name, u8 num_parents, struct clk *parent, struct clk *alt_parent,
440 struct clk *rockchip_clk_register_mmc(const char *name, const char *const *parent_names, u8 num_parents,
455 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, const char *const *parent_names, u8 num_parents,
461 struct clk *rockchip_clk_register_inverter(const char *name, const char *const *parent_names, u8 num_parents,
464 struct clk *rockchip_clk_register_muxgrf(const char *name, const char *const *parent_names, u8 num_parents, int flags,
491 u8 num_parents; member
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H A Dclk.c37 static struct clk *rockchip_clk_register_branch(const char *name, const char *const *parent_names, u8 num_parents, in rockchip_clk_register_branch() argument
51 if (num_parents > 1) { in rockchip_clk_register_branch()
100 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux ? &mux->hw : NULL, mux_ops, in rockchip_clk_register_branch()
222 const char *const *parent_names, u8 num_parents, in rockchip_clk_register_frac_branch()
271 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, NULL, NULL, &div->hw, div_ops, in rockchip_clk_register_frac_branch()
284 frac->mux_frac_idx = match_string(child->parent_names, child->num_parents, name); in rockchip_clk_register_frac_branch()
302 init.num_parents = child->num_parents; in rockchip_clk_register_frac_branch()
328 u8 num_parents, void __iomem *base, unsigned int mult, in rockchip_clk_register_factor_branch()
360 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, NUL in rockchip_clk_register_factor_branch()
221 rockchip_clk_register_frac_branch(struct rockchip_clk_provider *ctx, const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, struct rockchip_clk_branch *child, unsigned long max_prate, spinlock_t *lock) rockchip_clk_register_frac_branch() argument
327 rockchip_clk_register_factor_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, unsigned int mult, unsigned int div, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) rockchip_clk_register_factor_branch() argument
371 rockchip_clk_register_composite_brother_branch( struct rockchip_clk_provider *ctx, const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u32 *mux_table, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, struct rockchip_clk_branch *brother, spinlock_t *lock) rockchip_clk_register_composite_brother_branch() argument
610 rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, unsigned int lookup_id, const char *name, u8 num_parents, struct clk *parent, struct clk *alt_parent, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates) rockchip_clk_register_armclk() argument
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H A Dclk-ddr.c218 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, const char *const *parent_names, u8 num_parents, in rockchip_clk_register_ddrclk() argument
239 init.num_parents = num_parents; in rockchip_clk_register_ddrclk()
H A Dclk-half-divider.c148 struct clk *rockchip_clk_register_halfdiv(const char *name, const char *const *parent_names, u8 num_parents, in rockchip_clk_register_halfdiv() argument
160 if (num_parents > 1) { in rockchip_clk_register_halfdiv()
205 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux ? &mux->hw : NULL, mux_ops, in rockchip_clk_register_halfdiv()
H A Dclk-cpu.c245 struct clk *rockchip_clk_register_cpuclk(const char *name, u8 num_parents, struct clk *parent, struct clk *alt_parent, in rockchip_clk_register_cpuclk() argument
256 if (num_parents < 2) { in rockchip_clk_register_cpuclk()
274 init.num_parents = 1; in rockchip_clk_register_cpuclk()
H A Dclk-pll.c1198 const char *name, const char *const *parent_names, u8 num_parents, int con_offset, in rockchip_clk_register_pll()
1210 if ((pll_type != pll_rk3328 && num_parents != 0x2) || (pll_type == pll_rk3328 && num_parents != 0x1)) { in rockchip_clk_register_pll()
1251 init.num_parents = 0x2; in rockchip_clk_register_pll()
1253 init.num_parents = ARRAY_SIZE(pll_parents); in rockchip_clk_register_pll()
1272 init.num_parents = 1; in rockchip_clk_register_pll()
1197 rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, enum rockchip_pll_type pll_type, const char *name, const char *const *parent_names, u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, unsigned long flags, u8 clk_pll_flags) rockchip_clk_register_pll() argument
/device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/
H A Dclk.h418 * @num_parents: number of parents
436 u8 num_parents; member
456 .num_parents = ARRAY_SIZE(_pnames), \
469 u8 num_parents, int con_offset, int grf_lock_offset,
522 u8 num_parents,
529 const char *const *parent_names, u8 num_parents,
546 u8 num_parents, int mux_offset,
554 const char *const *parent_names, u8 num_parents,
559 const char *const *parent_names, u8 num_parents,
587 u8 num_parents; member
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/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk.h418 * @num_parents: number of parents
436 u8 num_parents; member
456 .num_parents = ARRAY_SIZE(_pnames), \
469 u8 num_parents, int con_offset, int grf_lock_offset,
522 u8 num_parents,
529 const char *const *parent_names, u8 num_parents,
546 u8 num_parents, int mux_offset,
554 const char *const *parent_names, u8 num_parents,
559 const char *const *parent_names, u8 num_parents,
587 u8 num_parents; member
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H A Dclk-dclk-divider.c93 u8 num_parents, in rockchip_clk_register_dclk_branch()
113 if (num_parents > 1) { in rockchip_clk_register_dclk_branch()
156 clk = clk_register_composite(NULL, name, parent_names, num_parents, in rockchip_clk_register_dclk_branch()
91 rockchip_clk_register_dclk_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, unsigned long max_prate, spinlock_t *lock) rockchip_clk_register_dclk_branch() argument
H A Dclk-link.c61 init.num_parents = 1; in register_clocks()
H A Dclk-pvtm.c176 init.num_parents = 0; in clock_pvtm_regitstor()
/device/soc/rockchip/common/sdk_linux/include/linux/
H A Dclk-provider.h273 * @num_parents: number of possible parents
283 u8 num_parents; member
776 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, const char *name, u8 num_parents,
781 u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
784 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, shift, width, clk_mux_flags, lock) \
785 clk_register_mux_table((dev), (name), (parent_names), (num_parents), (flags), (reg), (shift), BIT((width)) - 1, \
787 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, flags, reg, shift, mask, clk_mux_flags, table, \
789 __clk_hw_register_mux((dev), NULL, (name), (num_parents), (parent_names), NULL, NULL, (flags), (reg), (shift), \
791 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, shift, width, clk_mux_flags, lock) \
792 __clk_hw_register_mux((dev), NULL, (name), (num_parents), (parent_name
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/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c36 .branch_type = branch_mux, .name = (cname), .parent_names = (pnames), .num_parents = ARRAY_SIZE(pnames), \
43 .num_parents = 1, .flags = (f), \
49 .num_parents = 1, .flags = (f), .div_width = (w), \
56 u8 num_parents; member
280 init.num_parents = branch->num_parents; in vop2_clk_register()
286 init.num_parents = 0; in vop2_clk_register()
/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c40 .num_parents = ARRAY_SIZE(pnames), \
49 .num_parents = 1, \
58 .num_parents = 1, \
67 u8 num_parents; member
296 init.num_parents = branch->num_parents; in vop2_clk_register()
302 init.num_parents = 0; in vop2_clk_register()
/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-dclk-divider.c92 struct clk *rockchip_clk_register_dclk_branch(const char *name, const char *const *parent_names, u8 num_parents, in rockchip_clk_register_dclk_branch() argument
105 if (num_parents > 1) { in rockchip_clk_register_dclk_branch()
151 clk = clk_register_composite(NULL, name, parent_names, num_parents, mux ? &mux->hw : NULL, mux_ops, in rockchip_clk_register_dclk_branch()
H A Dclk-pvtm.c174 init.num_parents = 0; in clock_pvtm_regitstor()
/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c794 init.num_parents = 1; in rockchip_usb_phy_init()
798 init.num_parents = 0; in rockchip_usb_phy_init()
H A Dphy-rockchip-inno-usb2.c445 init.num_parents = 1; in rockchip_usb2phy_clk480m_register()
448 init.num_parents = 0; in rockchip_usb2phy_clk480m_register()
/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-inno-hdmi-phy.c753 init.num_parents = 1; in inno_hdmi_phy_clk_register()
/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi-phy.c648 init.num_parents = 1; in inno_hdmi_phy_clk_register()
H A Dphy-rockchip-samsung-hdptx-hdmi.c1984 init.num_parents = 1; in rockchip_hdptx_phy_clk_register()

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