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/device/soc/hisilicon/hi3751v350/sdk_linux/source/common/drv/include/
H A Dosal_ioctl.h65 #define _IOC(dir, type, nr, size) \
68 ((nr) << _IOC_NRSHIFT) | \
86 #define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
87 #define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
88 #define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
89 #define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHEC
[all...]
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/osal/include/
H A Dosal_ioctl.h99 #define _IOC(dir, type, nr, size) \
102 ((nr) << _IOC_NRSHIFT) | \
120 #define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
124 #define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
128 #define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
132 #define _IOWR(type, nr, size) _IOC(_IOC_READ | _IOC_WRITE, (type), (nr), (_IOC_TYPECHEC
[all...]
/device/soc/hisilicon/hi3516dv300/sdk_linux/include/
H A Dosal_ioctl.h96 #define _IOC(dir, type, nr, size) \
99 ((nr) << _IOC_NRSHIFT) | \
117 #define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
121 #define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
125 #define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
129 #define _IOWR(type, nr, size) _IOC(_IOC_READ | _IOC_WRITE, (type), (nr), (_IOC_TYPECHEC
[all...]
/device/soc/hisilicon/hi3516dv300/sdk_liteos/include/
H A Dosal_ioctl.h96 #define _IOC(dir, type, nr, size) \
99 ((nr) << _IOC_NRSHIFT) | \
117 #define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
121 #define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
125 #define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
129 #define _IOWR(type, nr, size) _IOC(_IOC_READ | _IOC_WRITE, (type), (nr), (_IOC_TYPECHEC
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/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/common/
H A Dmali_osk_bitops.h87 * @param nr bit number to clear, starting from the (Little-endian) least
91 MALI_STATIC_INLINE void _mali_osk_clear_nonatomic_bit(u32 nr, u32 *addr)
93 addr += nr >> 5; /* find the correct word */
94 nr = nr & ((1 << 5) - 1); /* The bit number within the word */
96 _mali_internal_clear_bit(nr, addr);
100 * @param nr bit number to set, starting from the (Little-endian) least
104 MALI_STATIC_INLINE void _mali_osk_set_nonatomic_bit(u32 nr, u32 *addr)
106 addr += nr >> 5; /* find the correct word */
107 nr
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/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/common/
H A Dmali_osk_bitops.h89 * @param nr bit number to clear, starting from the (Little-endian) least
93 MALI_STATIC_INLINE void _mali_osk_clear_nonatomic_bit(u32 nr, u32 *addr)
95 addr += nr >> UINT32_BITS_NONATOMICB_BIT; /* find the correct word */
96 nr = nr & ((1 << UINT32_BITS_NONATOMICB_BIT) - 1); /* The bit number within the word */
98 _mali_internal_clear_bit(nr, addr);
102 * @param nr bit number to set, starting from the (Little-endian) least
106 MALI_STATIC_INLINE void _mali_osk_set_nonatomic_bit(u32 nr, u32 *addr)
108 addr += nr >> UINT32_BITS_NONATOMICB_BIT; /* find the correct word */
109 nr
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/oal/
H A Doal_atomic.h75 #define oal_bit_atomic_for_each_set(nr, p_addr, size) for_each_set_bit(nr, p_addr, size)
80 #define IS_BIT_SET(nr) (1UL << ((nr) % BITS_PER_LONG))
81 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
82 #define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
395 static inline hi_void oal_bit_atomic_set(hi_s32 nr, HI_VOLATILE oal_bitops *p_addr) in oal_bit_atomic_set() argument
398 set_bit(nr, p_add in oal_bit_atomic_set()
411 oal_bit_atomic_test(hi_s32 nr, HI_VOLATILE const oal_bitops *p_addr) oal_bit_atomic_test() argument
427 oal_bit_atomic_test_and_set(hi_s32 nr, HI_VOLATILE oal_bitops *p_addr) oal_bit_atomic_test_and_set() argument
445 oal_bit_atomic_test_and_clear(hi_u32 nr, HI_VOLATILE oal_bitops *p_addr) oal_bit_atomic_test_and_clear() argument
470 oal_bit_atomic_clear(hi_s32 nr, HI_VOLATILE oal_bitops *p_addr) oal_bit_atomic_clear() argument
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/
H A Dmali_kbase_tlstream.h101 void __kbase_tlstream_tl_summary_new_ctx(void *context, u32 nr, u32 tgid);
103 void __kbase_tlstream_tl_summary_new_lpu(void *lpu, u32 nr, u32 fn);
105 void __kbase_tlstream_tl_summary_new_as(void *as, u32 nr);
107 void __kbase_tlstream_tl_new_ctx(void *context, u32 nr, u32 tgid);
108 void __kbase_tlstream_tl_new_atom(void *atom, u32 nr);
174 * @nr: context number
182 #define KBASE_TLSTREAM_TL_SUMMARY_NEW_CTX(context, nr, tgid) __TRACE_IF_ENABLED(tl_summary_new_ctx, context, nr, tgid)
200 * @nr: sequential number assigned to this LPU
208 #define KBASE_TLSTREAM_TL_SUMMARY_NEW_LPU(lpu, nr, f
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H A Dmali_kbase_mmu.c57 * @nr: The number of pages to flush.
71 static void kbase_mmu_flush_invalidate(struct kbase_context *kctx, u64 vpfn, size_t nr, bool sync);
526 static void mmu_insert_pages_failure_recovery(struct kbase_context *kctx, u64 vpfn, size_t nr) in mmu_insert_pages_failure_recovery() argument
542 while (nr) { in mmu_insert_pages_failure_recovery()
548 if (count > nr) { in mmu_insert_pages_failure_recovery()
549 count = nr; in mmu_insert_pages_failure_recovery()
566 nr -= count; in mmu_insert_pages_failure_recovery()
575 * Map the single page 'phys' 'nr' of times, starting at GPU PFN 'vpfn'
577 int kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, phys_addr_t phys, size_t nr, unsigned long flags) in kbase_mmu_insert_single_page() argument
586 size_t remain = nr; in kbase_mmu_insert_single_page()
682 kbase_mmu_insert_pages_no_flush(struct kbase_context *kctx, u64 vpfn, phys_addr_t *phys, size_t nr, unsigned long flags) kbase_mmu_insert_pages_no_flush() argument
791 kbase_mmu_insert_pages(struct kbase_context *kctx, u64 vpfn, phys_addr_t *phys, size_t nr, unsigned long flags) kbase_mmu_insert_pages() argument
813 kbase_mmu_flush_invalidate_noretain(struct kbase_context *kctx, u64 vpfn, size_t nr, bool sync) kbase_mmu_flush_invalidate_noretain() argument
856 kbase_mmu_flush_invalidate(struct kbase_context *kctx, u64 vpfn, size_t nr, bool sync) kbase_mmu_flush_invalidate() argument
989 kbase_mmu_teardown_pages(struct kbase_context *kctx, u64 vpfn, size_t nr) kbase_mmu_teardown_pages() argument
1072 kbase_mmu_update_pages(struct kbase_context *kctx, u64 vpfn, phys_addr_t *phys, size_t nr, unsigned long flags) kbase_mmu_update_pages() argument
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/
H A Dmali_kbase_tlstream.h109 void __kbase_tlstream_tl_summary_new_ctx(void *context, u32 nr, u32 tgid);
111 void __kbase_tlstream_tl_summary_new_lpu(void *lpu, u32 nr, u32 fn);
113 void __kbase_tlstream_tl_summary_new_as(void *as, u32 nr);
115 void __kbase_tlstream_tl_new_ctx(void *context, u32 nr, u32 tgid);
116 void __kbase_tlstream_tl_new_atom(void *atom, u32 nr);
186 * @nr: context number
194 #define KBASE_TLSTREAM_TL_SUMMARY_NEW_CTX(context, nr, tgid) \
195 __TRACE_IF_ENABLED(tl_summary_new_ctx, context, nr, tgid)
213 * @nr: sequential number assigned to this LPU
221 #define KBASE_TLSTREAM_TL_SUMMARY_NEW_LPU(lpu, nr, f
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H A Dmali_kbase_mmu.c52 * @nr: The number of pages to flush.
67 u64 vpfn, size_t nr, bool sync);
564 size_t nr) in mmu_insert_pages_failure_recovery()
580 while (nr) { in mmu_insert_pages_failure_recovery()
586 if (count > nr) in mmu_insert_pages_failure_recovery()
587 count = nr; in mmu_insert_pages_failure_recovery()
602 nr -= count; in mmu_insert_pages_failure_recovery()
611 * Map the single page 'phys' 'nr' of times, starting at GPU PFN 'vpfn'
614 phys_addr_t phys, size_t nr, in kbase_mmu_insert_single_page()
624 size_t remain = nr; in kbase_mmu_insert_single_page()
563 mmu_insert_pages_failure_recovery(struct kbase_context *kctx, u64 vpfn, size_t nr) mmu_insert_pages_failure_recovery() argument
613 kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, phys_addr_t phys, size_t nr, unsigned long flags) kbase_mmu_insert_single_page() argument
725 kbase_mmu_insert_pages_no_flush(struct kbase_context *kctx, u64 vpfn, phys_addr_t *phys, size_t nr, unsigned long flags) kbase_mmu_insert_pages_no_flush() argument
840 kbase_mmu_insert_pages(struct kbase_context *kctx, u64 vpfn, phys_addr_t *phys, size_t nr, unsigned long flags) kbase_mmu_insert_pages() argument
864 kbase_mmu_flush_invalidate_noretain(struct kbase_context *kctx, u64 vpfn, size_t nr, bool sync) kbase_mmu_flush_invalidate_noretain() argument
907 kbase_mmu_flush_invalidate(struct kbase_context *kctx, u64 vpfn, size_t nr, bool sync) kbase_mmu_flush_invalidate() argument
1042 kbase_mmu_teardown_pages(struct kbase_context *kctx, u64 vpfn, size_t nr) kbase_mmu_teardown_pages() argument
1125 kbase_mmu_update_pages(struct kbase_context *kctx, u64 vpfn, phys_addr_t *phys, size_t nr, unsigned long flags) kbase_mmu_update_pages() argument
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/mmu/
H A Dmali_kbase_mmu.h107 struct tagged_addr *phys, size_t nr, unsigned long flags, int group_id);
109 size_t nr, unsigned long flags, int as_nr, int group_id);
110 int kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, struct tagged_addr phys, size_t nr,
113 int kbase_mmu_teardown_pages(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, u64 vpfn, size_t nr, int as_nr);
114 int kbase_mmu_update_pages(struct kbase_context *kctx, u64 vpfn, struct tagged_addr *phys, size_t nr,
H A Dmali_kbase_mmu.c56 * @nr: The number of pages to flush.
70 static void kbase_mmu_flush_invalidate(struct kbase_context *kctx, u64 vpfn, size_t nr, bool sync);
76 * @nr: The number of pages to flush.
82 static void kbase_mmu_flush_invalidate_no_ctx(struct kbase_device *kbdev, u64 vpfn, size_t nr, bool sync, int as_nr);
112 static int kbase_mmu_update_pages_no_flush(struct kbase_context *kctx, u64 vpfn, struct tagged_addr *phys, size_t nr,
194 u64 start_pfn, size_t nr, u32 op) in kbase_gpu_mmu_handle_write_faulting_as()
199 kbase_mmu_hw_do_operation(kbdev, faulting_as, start_pfn, nr, op, 1); in kbase_gpu_mmu_handle_write_faulting_as()
1099 * Map the single page 'phys' 'nr' of times, starting at GPU PFN 'vpfn'
1101 int kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, struct tagged_addr phys, size_t nr, in kbase_mmu_insert_single_page() argument
1112 size_t remain = nr; in kbase_mmu_insert_single_page()
193 kbase_gpu_mmu_handle_write_faulting_as(struct kbase_device *kbdev, struct kbase_as *faulting_as, u64 start_pfn, size_t nr, u32 op) kbase_gpu_mmu_handle_write_faulting_as() argument
1248 kbase_mmu_insert_pages_no_flush(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, const u64 start_vpfn, struct tagged_addr *phys, size_t nr, unsigned long flags, int const group_id) kbase_mmu_insert_pages_no_flush() argument
1379 kbase_mmu_insert_pages(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, u64 vpfn, struct tagged_addr *phys, size_t nr, unsigned long flags, int as_nr, int const group_id) kbase_mmu_insert_pages() argument
1408 kbase_mmu_flush_invalidate_noretain(struct kbase_context *kctx, u64 vpfn, size_t nr, bool sync) kbase_mmu_flush_invalidate_noretain() argument
1440 kbase_mmu_flush_invalidate_as(struct kbase_device *kbdev, struct kbase_as *as, u64 vpfn, size_t nr, bool sync) kbase_mmu_flush_invalidate_as() argument
1478 kbase_mmu_flush_invalidate_no_ctx(struct kbase_device *kbdev, u64 vpfn, size_t nr, bool sync, int as_nr) kbase_mmu_flush_invalidate_no_ctx() argument
1486 kbase_mmu_flush_invalidate(struct kbase_context *kctx, u64 vpfn, size_t nr, bool sync) kbase_mmu_flush_invalidate() argument
1568 kbase_mmu_teardown_pages(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, u64 vpfn, size_t nr, int as_nr) kbase_mmu_teardown_pages() argument
1707 kbase_mmu_update_pages_no_flush(struct kbase_context *kctx, u64 vpfn, struct tagged_addr *phys, size_t nr, unsigned long flags, int const group_id) kbase_mmu_update_pages_no_flush() argument
1786 kbase_mmu_update_pages(struct kbase_context *kctx, u64 vpfn, struct tagged_addr *phys, size_t nr, unsigned long flags, int const group_id) kbase_mmu_update_pages() argument
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/mmu/
H A Dmali_kbase_mmu.h133 struct tagged_addr *phys, size_t nr,
137 struct tagged_addr *phys, size_t nr,
141 struct tagged_addr phys, size_t nr,
147 size_t nr, int as_nr);
149 struct tagged_addr *phys, size_t nr,
H A Dmali_kbase_mmu.c132 * @nr: The number of pages to flush.
148 kbase_mmu_flush_invalidate(struct kbase_context *kctx, u64 vpfn, size_t nr,
156 * @nr: The number of pages to flush.
164 struct kbase_device *kbdev, u64 vpfn, size_t nr, bool sync, int as_nr,
196 struct tagged_addr *phys, size_t nr,
306 u64 start_pfn, size_t nr, in kbase_gpu_mmu_handle_write_faulting_as()
323 .nr = nr, in kbase_gpu_mmu_handle_write_faulting_as()
874 .nr = 0, in kbase_mmu_page_fault_worker()
909 .nr in kbase_mmu_page_fault_worker()
304 kbase_gpu_mmu_handle_write_faulting_as(struct kbase_device *kbdev, struct kbase_as *faulting_as, u64 start_pfn, size_t nr, u32 kctx_id) kbase_gpu_mmu_handle_write_faulting_as() argument
1368 kbase_mmu_insert_single_page(struct kbase_context *kctx, u64 vpfn, struct tagged_addr phys, size_t nr, unsigned long flags, int const group_id, enum kbase_caller_mmu_sync_info mmu_sync_info) kbase_mmu_insert_single_page() argument
1541 kbase_mmu_insert_pages_no_flush(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, const u64 start_vpfn, struct tagged_addr *phys, size_t nr, unsigned long flags, int const group_id) kbase_mmu_insert_pages_no_flush() argument
1697 kbase_mmu_insert_pages(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, u64 vpfn, struct tagged_addr *phys, size_t nr, unsigned long flags, int as_nr, int const group_id, enum kbase_caller_mmu_sync_info mmu_sync_info) kbase_mmu_insert_pages() argument
1730 kbase_mmu_flush_invalidate_noretain(struct kbase_context *kctx, u64 vpfn, size_t nr) kbase_mmu_flush_invalidate_noretain() argument
1777 kbase_mmu_flush_invalidate_as(struct kbase_device *kbdev, struct kbase_as *as, u64 vpfn, size_t nr, bool sync, u32 kctx_id, enum kbase_caller_mmu_sync_info mmu_sync_info) kbase_mmu_flush_invalidate_as() argument
1850 kbase_mmu_flush_invalidate_no_ctx(struct kbase_device *kbdev, u64 vpfn, size_t nr, bool sync, int as_nr, enum kbase_caller_mmu_sync_info mmu_sync_info) kbase_mmu_flush_invalidate_no_ctx() argument
1863 kbase_mmu_flush_invalidate(struct kbase_context *kctx, u64 vpfn, size_t nr, bool sync, enum kbase_caller_mmu_sync_info mmu_sync_info) kbase_mmu_flush_invalidate() argument
2001 kbase_mmu_teardown_pages(struct kbase_device *kbdev, struct kbase_mmu_table *mmut, u64 vpfn, size_t nr, int as_nr) kbase_mmu_teardown_pages() argument
2174 kbase_mmu_update_pages_no_flush(struct kbase_context *kctx, u64 vpfn, struct tagged_addr *phys, size_t nr, unsigned long flags, int const group_id) kbase_mmu_update_pages_no_flush() argument
2275 kbase_mmu_update_pages(struct kbase_context *kctx, u64 vpfn, struct tagged_addr *phys, size_t nr, unsigned long flags, int const group_id) kbase_mmu_update_pages() argument
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/
H A Ddrm_ioctl.c810 unsigned int nr = DRM_IOCTL_NR(cmd); in drm_ioctl() local
827 is_driver_ioctl = nr >= DRM_COMMAND_BASE && nr < DRM_COMMAND_END; in drm_ioctl()
831 unsigned int index = nr - DRM_COMMAND_BASE; in drm_ioctl()
840 if (nr >= DRM_CORE_IOCTL_COUNT) { in drm_ioctl()
843 nr = array_index_nospec(nr, DRM_CORE_IOCTL_COUNT); in drm_ioctl()
844 ioctl = &drm_ioctls[nr]; in drm_ioctl()
895 DRM_DEBUG("invalid ioctl: comm=\"%s\", pid=%d, dev=0x%lx, auth=%d, cmd=0x%02x, nr=0x%02x\n", current->comm, in drm_ioctl()
897 cmd, nr); in drm_ioctl()
922 drm_ioctl_flags(unsigned int nr, unsigned int *flags) drm_ioctl_flags() argument
[all...]
/device/soc/rockchip/common/hardware/mpp/include/
H A Dvcodec_service.h32 #define VPU_IOC_WRITE(nr, size) _IOC(_IOC_WRITE, VPU_IOC_MAGIC, (nr), (size))
/device/soc/rockchip/rk3399/hardware/mpp/include/
H A Dvcodec_service.h32 #define VPU_IOC_WRITE(nr, size) _IOC(_IOC_WRITE, VPU_IOC_MAGIC, (nr), (size))
/device/soc/rockchip/rk3568/hardware/mpp/include/
H A Dvcodec_service.h32 #define VPU_IOC_WRITE(nr, size) _IOC(_IOC_WRITE, VPU_IOC_MAGIC, (nr), (size))
/device/soc/rockchip/rk3588/hardware/mpp/include/
H A Dvcodec_service.h33 #define VPU_IOC_WRITE(nr, size) _IOC(_IOC_WRITE, VPU_IOC_MAGIC, (nr), (size))
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/include/
H A Dplatform.h24 #define BIT(nr) (1 << (nr))
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/include/
H A Dplatform.h24 #define BIT(nr) (1 << (nr))
/device/soc/rockchip/common/sdk_linux/include/dt-bindings/suspend/
H A Drockchip-rk3568.h14 #define BIT(nr) (1 << (nr))
/device/soc/rockchip/rk3588/kernel/include/dt-bindings/suspend/
H A Drockchip-rk3588.h14 #define BIT(nr) (1 << (nr))
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/include/
H A Ddrv_cipher_kapi.h111 #define crypto_ioc(dir, type, nr, size) \
112 (((dir) << 30) | ((size) << 16) | ((type) << 8) | ((nr) << 0))
114 #define crypto_ior(nr, size) crypto_ioc(CRYPTO_IOC_R, HI_ID_CIPHER, (nr), size)
115 #define crypto_iow(nr, size) crypto_ioc(CRYPTO_IOC_W, HI_ID_CIPHER, (nr), size)
116 #define crypto_iowr(nr, size) crypto_ioc(CRYPTO_IOC_RW, HI_ID_CIPHER, (nr), size)

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