mux_gpll_xin24m_p (reference) in projects: device - OpenGrok search results

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Searched refs:mux_gpll_xin24m_p (Results 1 - 2 of 2) sorted by relevance

/device/soc/rockchip/common/vendor/drivers/clk/
H A D	clk-rk1808.c	153 PNAME(mux_gpll_xin24m_p) = {"gpll", "xin24m"}; variable 650 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS, 652 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS, 654 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS, 656 COMPOSITE(SCLK_I2C4, "clk_i2c4", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 7, DFLAGS, 658 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(71), 15, 1, MFLAGS, 8, 7, DFLAGS, 661 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS, 663 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS, 665 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS, 687 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, [all...]
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A D	clk-px30.c	114 PNAME(mux_gpll_xin24m_p) = {"gpll", "xin24m"}; variable 313 COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS, 514 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS, 516 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS, 518 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS, 520 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS, 522 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS, 524 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS, 526 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS, 528 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, [all...]

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