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/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/common/
H A Dmali_pmu.c65 void mali_pmu_set_registered_cores_mask(struct mali_pmu_core *pmu, u32 mask) in mali_pmu_set_registered_cores_mask() argument
67 pmu->registered_cores_mask = mask; in mali_pmu_set_registered_cores_mask()
98 mali_osk_errcode_t mali_pmu_power_down(struct mali_pmu_core *pmu, u32 mask) in mali_pmu_power_down() argument
105 MALI_DEBUG_ASSERT(mask <= pmu->registered_cores_mask); in mali_pmu_power_down()
110 ("PMU power down: ...................... [%s]\n", mali_pm_mask_to_string(mask))); in mali_pmu_power_down()
118 MALI_DEBUG_ASSERT((stat & mask) == 0); in mali_pmu_power_down()
120 mask &= ~(0x1 << MALI_DOMAIN_INDEX_DUMMY); in mali_pmu_power_down()
122 if (mask == 0 || ((~stat) & mask) == 0) { in mali_pmu_power_down()
126 mali_hw_core_register_write(&pmu->hw_core, PMU_REG_ADDR_MGMT_POWER_DOWN, mask); in mali_pmu_power_down()
167 mali_pmu_power_up(struct mali_pmu_core *pmu, u32 mask) mali_pmu_power_up() argument
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H A Dmali_pm.c36 /* the wanted domain mask (protected by pm_lock_state) */
65 * because we mush store the mask of different pp cores: 0, 1, 2, 3, 4, 5, 6, 7, 8.
89 const char *mali_pm_mask_to_string(u32 mask);
230 MALI_DEBUG_PRINT(MALI_KERNEL_LEVEL_MESSAGE, ("PM: wanted domain mask = 0x%08X (get refs)\n", pd_mask_wanted)); in mali_pm_get_domain_refs()
239 u32 mask = 0; in mali_pm_put_domain_refs() local
247 mask |= mali_pm_domain_ref_put(domains[i]); in mali_pm_put_domain_refs()
250 if (mask == 0) { in mali_pm_put_domain_refs()
255 MALI_DEBUG_ASSERT((pd_mask_wanted & mask) == mask); in mali_pm_put_domain_refs()
257 /* Update our desired domain mask */ in mali_pm_put_domain_refs()
998 u32 mask = 0; mali_pm_get_registered_cores_mask() local
1035 mali_pm_mask_to_string(u32 mask) mali_pm_mask_to_string() argument
1092 mali_pm_stat_from_mask(u32 mask, u32 *num_pp, u32 *cost) mali_pm_stat_from_mask() argument
1166 u32 num_pp, cost, mask; mali_pm_power_cost_setup() local
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H A Dmali_pmu.h24 /** @brief MALI inbuilt PMU hardware info and PMU hardware has knowledge of cores power mask
38 PMU_REG_ADDR_MGMT_INT_MASK = 0x0C, /* < Interrupt mask register */
68 /** @brief Set registered cores mask
71 * @param mask All available/valid domain bits
73 void mali_pmu_set_registered_cores_mask(struct mali_pmu_core *pmu, u32 mask);
94 /** @brief Returns a mask of the currently powered up domains
109 * @param mask Mask specifying which power domains to power down
112 mali_osk_errcode_t mali_pmu_power_down(struct mali_pmu_core *pmu, u32 mask);
119 * @param mask Mask specifying which power domains to power up
122 mali_osk_errcode_t mali_pmu_power_up(struct mali_pmu_core *pmu, u32 mask);
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/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/common/
H A Dmali_pmu.c68 void mali_pmu_set_registered_cores_mask(struct mali_pmu_core *pmu, u32 mask) in mali_pmu_set_registered_cores_mask() argument
70 pmu->registered_cores_mask = mask; in mali_pmu_set_registered_cores_mask()
121 _mali_osk_errcode_t mali_pmu_power_down(struct mali_pmu_core *pmu, u32 mask) in mali_pmu_power_down() argument
128 MALI_DEBUG_ASSERT(mask <= pmu->registered_cores_mask); in mali_pmu_power_down()
135 mali_pm_mask_to_string(mask))); in mali_pmu_power_down()
144 MALI_DEBUG_ASSERT(0 == (stat & mask)); in mali_pmu_power_down()
146 mask &= ~(0x1 << MALI_DOMAIN_INDEX_DUMMY); in mali_pmu_power_down()
148 if (0 == mask || 0 == ((~stat) & mask)) return _MALI_OSK_ERR_OK; in mali_pmu_power_down()
151 PMU_REG_ADDR_MGMT_POWER_DOWN, mask); in mali_pmu_power_down()
178 mali_pmu_power_up(struct mali_pmu_core *pmu, u32 mask) mali_pmu_power_up() argument
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H A Dmali_pm.c35 /* the wanted domain mask (protected by pm_lock_state) */
66 *because we mush store the mask of different pp cores: 0, 1, 2, 3, 4, 5, 6, 7, 8.
90 const char *mali_pm_mask_to_string(u32 mask);
240 MALI_DEBUG_PRINT(3, ("PM: wanted domain mask = 0x%08X (get refs)\n", pd_mask_wanted)); in mali_pm_get_domain_refs()
250 u32 mask = 0; in mali_pm_put_domain_refs() local
258 mask |= mali_pm_domain_ref_put(domains[i]); in mali_pm_put_domain_refs()
261 if (0 == mask) { in mali_pm_put_domain_refs()
266 MALI_DEBUG_ASSERT((pd_mask_wanted & mask) == mask); in mali_pm_put_domain_refs()
268 /* Update our desired domain mask */ in mali_pm_put_domain_refs()
1068 u32 mask = 0; mali_pm_get_registered_cores_mask() local
1106 mali_pm_mask_to_string(u32 mask) mali_pm_mask_to_string() argument
1164 mali_pm_stat_from_mask(u32 mask, u32 *num_pp, u32 *cost) mali_pm_stat_from_mask() argument
1239 u32 num_pp, cost, mask; mali_pm_power_cost_setup() local
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H A Dmali_pmu.h23 /** @brief MALI inbuilt PMU hardware info and PMU hardware has knowledge of cores power mask
37 PMU_REG_ADDR_MGMT_INT_MASK = 0x0C, /*< Interrupt mask register */
67 /** @brief Set registered cores mask
70 * @param mask All available/valid domain bits
72 void mali_pmu_set_registered_cores_mask(struct mali_pmu_core *pmu, u32 mask);
93 /** @brief Returns a mask of the currently powered up domains
108 * @param mask Mask specifying which power domains to power down
111 _mali_osk_errcode_t mali_pmu_power_down(struct mali_pmu_core *pmu, u32 mask);
118 * @param mask Mask specifying which power domains to power up
121 _mali_osk_errcode_t mali_pmu_power_up(struct mali_pmu_core *pmu, u32 mask);
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/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dsiutils.h137 #define GPIO_REGEVT_INTMSK 1 /**< GPIO register event int mask */
192 /* External BT Coex enable mask */
194 /* External PA enable mask */
196 /* WL/BT control enable mask */
249 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
250 extern uint si_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
251 extern uint si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val);
254 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
255 extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val);
257 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint3
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/device/qemu/SmartL_E802/liteos_m/board/hals/csky_driver/src/
H A Ddw_gpio.c52 uint32_t mask; ///< gpio mask bit member
80 gpio_reg->SWPORT_DDR &= (~gpio_priv->mask); in gpio_set_direction()
82 gpio_reg->SWPORT_DDR |= gpio_priv->mask; in gpio_set_direction()
114 static int32_t gpio_write(void *port, uint32_t mask) in gpio_write() argument
121 value &= ~(mask); in gpio_write()
142 uint32_t mask = 1 << offset; in gpio_set_irq_mode() local
147 gpio_control_reg->INTTYPE_LEVEL |= mask; in gpio_set_irq_mode()
148 gpio_control_reg->INT_POLARITY |= mask; in gpio_set_irq_mode()
153 gpio_control_reg->INTTYPE_LEVEL |= mask; in gpio_set_irq_mode()
354 csi_gpio_port_config(gpio_port_handle_t handle, uint32_t mask, gpio_mode_e mode, gpio_direction_e dir) csi_gpio_port_config() argument
390 csi_gpio_port_write(gpio_port_handle_t handle, uint32_t mask, uint32_t value) csi_gpio_port_write() argument
411 csi_gpio_port_read(gpio_port_handle_t handle, uint32_t mask, uint32_t *value) csi_gpio_port_read() argument
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/device/soc/rockchip/common/sdk_linux/drivers/mfd/
H A Drk808.c29 int mask; member
356 /* set write mask bit 1, otherwise 'is_enabled()' get wrong status */
388 .mask = RK805_IRQ_PWRON_RISE_MSK,
393 .mask = RK805_IRQ_VB_LOW_MSK,
398 .mask = RK805_IRQ_PWRON_MSK,
403 .mask = RK805_IRQ_PWRON_LP_MSK,
408 .mask = RK805_IRQ_HOTDIE_MSK,
413 .mask = RK805_IRQ_RTC_ALARM_MSK,
418 .mask = RK805_IRQ_RTC_PERIOD_MSK,
423 .mask
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/device/soc/hisilicon/common/platform/pwm/
H A Dpwm_hi35xx.h72 uint32_t mask; in HiPwmOutputNumberSquareWaves() local
76 mask = ~(1 << PWM_KEEP_OFFSET); in HiPwmOutputNumberSquareWaves()
77 reg->ctrl &= mask; in HiPwmOutputNumberSquareWaves()
83 uint32_t mask; in HiPwmSetPolarity() local
85 mask = ~(1 << PWM_INV_OFFSET); in HiPwmSetPolarity()
86 reg->ctrl &= mask; in HiPwmSetPolarity()
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_boot.c47 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
50 uart_early_put_hex(mask); in ddr_training_error()
132 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
137 switch (mask) { in ddr_training_error()
247 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
H A Dddr_training_custom.h101 #define DDR_TRAINING_SAVE_REG_FUNC(relate_reg, mask) \
102 ddr_training_save_reg_custom(relate_reg, mask)
113 void ddr_training_save_reg_custom(void *relate_reg, unsigned int mask);
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_boot.c47 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
50 uart_early_put_hex(mask); in ddr_training_error()
132 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
137 switch (mask) { in ddr_training_error()
247 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
H A Dddr_training_custom.h99 #define DDR_TRAINING_SAVE_REG_FUNC(relate_reg, mask) \
100 ddr_training_save_reg_custom(relate_reg, mask)
109 void ddr_training_save_reg_custom(void *relate_reg, unsigned int mask);
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Dcommon.h154 void rkisp_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct);
155 void rkisp_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct);
160 void rkisp_next_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct);
161 void rkisp_next_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct);
171 static inline void rkisp_unite_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct, in rkisp_unite_set_bits() argument
174 rkisp_set_bits(dev, reg, mask, val, is_direct); in rkisp_unite_set_bits()
176 rkisp_next_set_bits(dev, reg, mask, val, is_direct); in rkisp_unite_set_bits()
180 static inline void rkisp_unite_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct, bool is_unite) in rkisp_unite_clear_bits() argument
182 rkisp_clear_bits(dev, reg, mask, is_direct); in rkisp_unite_clear_bits()
184 rkisp_next_clear_bits(dev, reg, mask, is_direc in rkisp_unite_clear_bits()
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/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/
H A Dcommon.h165 void rkisp_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct);
166 void rkisp_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct);
171 void rkisp_next_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct);
172 void rkisp_next_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct);
183 rkisp_unite_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, in rkisp_unite_set_bits() argument
186 rkisp_set_bits(dev, reg, mask, val, is_direct); in rkisp_unite_set_bits()
188 rkisp_next_set_bits(dev, reg, mask, val, is_direct); in rkisp_unite_set_bits()
192 rkisp_unite_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, in rkisp_unite_clear_bits() argument
195 rkisp_clear_bits(dev, reg, mask, is_direct); in rkisp_unite_clear_bits()
197 rkisp_next_clear_bits(dev, reg, mask, is_direc in rkisp_unite_clear_bits()
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/device/soc/rockchip/common/vendor/drivers/gpio/
H A Dgpio-rockchip.c377 u32 mask = BIT(d->hwirq); in rockchip_irq_set_type() local
404 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
408 bank->toggle_edge_mode |= mask; in rockchip_irq_set_type()
409 level |= mask; in rockchip_irq_set_type()
416 if (data & mask) { in rockchip_irq_set_type()
417 polarity &= ~mask; in rockchip_irq_set_type()
419 polarity |= mask; in rockchip_irq_set_type()
424 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
425 level |= mask; in rockchip_irq_set_type()
426 polarity |= mask; in rockchip_irq_set_type()
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/device/soc/rockchip/common/sdk_linux/drivers/gpio/
H A Dgpio-rockchip.c380 u32 mask = BIT(d->hwirq); in rockchip_irq_set_type() local
407 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
411 bank->toggle_edge_mode |= mask; in rockchip_irq_set_type()
412 level |= mask; in rockchip_irq_set_type()
419 if (data & mask) { in rockchip_irq_set_type()
420 polarity &= ~mask; in rockchip_irq_set_type()
422 polarity |= mask; in rockchip_irq_set_type()
427 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
428 level |= mask; in rockchip_irq_set_type()
429 polarity |= mask; in rockchip_irq_set_type()
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/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/
H A Dsiutils.c1419 si_core_cflags(si_t *sih, uint32 mask, uint32 val) in si_core_cflags() argument
1422 return sb_core_cflags(sih, mask, val); in si_core_cflags()
1426 return ai_core_cflags(sih, mask, val); in si_core_cflags()
1428 return ub_core_cflags(sih, mask, val); in si_core_cflags()
1436 si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val) in si_core_cflags_wo() argument
1439 sb_core_cflags_wo(sih, mask, val); in si_core_cflags_wo()
1443 ai_core_cflags_wo(sih, mask, val); in si_core_cflags_wo()
1445 ub_core_cflags_wo(sih, mask, val); in si_core_cflags_wo()
1451 si_core_sflags(si_t *sih, uint32 mask, uint32 val) in si_core_sflags() argument
1454 return sb_core_sflags(sih, mask, va in si_core_sflags()
1501 si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val) si_wrapperreg() argument
1614 si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) si_corereg() argument
1631 si_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) si_corereg_writeonly() argument
1651 si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val) si_pmu_corereg() argument
2216 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority) si_gpiocontrol() argument
2238 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority) si_gpioouten() argument
2260 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority) si_gpioout() argument
2350 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority) si_gpiointpolarity() argument
2367 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority) si_gpiointmask() argument
2383 si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority) si_gpioeventintmask() argument
2398 si_gpioled(si_t *sih, uint32 mask, uint32 val) si_gpioled() argument
2409 si_gpiotimerval(si_t *sih, uint32 mask, uint32 gpiotimerval) si_gpiotimerval() argument
2419 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val) si_gpiopull() argument
2431 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val) si_gpioevent() argument
3320 si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val) si_core_wrapperreg() argument
3347 uint32 mask; si_pmu_res_req_timer_clr() local
3586 si_srpwr_request(si_t *sih, uint32 mask, uint32 val) si_srpwr_request() argument
3639 si_srpwr_stat_spinwait(si_t *sih, uint32 mask, uint32 val) si_srpwr_stat_spinwait() argument
3709 uint32 mask = SRPWR_DMN0_PCIE_MASK | si_srpwr_domain_all_mask() local
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/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/oal/
H A Doal_atomic.h403 const oal_bitops mask = IS_BIT_SET(nr); in oal_bit_atomic_set()
405 *p |= mask; in oal_bit_atomic_set()
435 oal_bitops mask = IS_BIT_SET(nr); in oal_bit_atomic_test_and_set()
438 *p = old | mask; in oal_bit_atomic_test_and_set()
441 return ((old & mask) != 0); in oal_bit_atomic_test_and_set()
453 oal_bitops mask = IS_BIT_SET(nr); in oal_bit_atomic_test_and_clear()
456 *p = old & ~mask; in oal_bit_atomic_test_and_clear()
459 return (old & mask) != 0; in oal_bit_atomic_test_and_clear()
478 const oal_bitops mask = IS_BIT_SET(nr); in oal_bit_atomic_clear()
480 *p &= ~mask; in oal_bit_atomic_clear()
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/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/cif/
H A Dregs.h514 unsigned int mask; \
517 mask = 0x1 << 0; \
520 mask = 0x1 << ((id) + 10); \
523 mask; \
530 unsigned int mask; \
533 mask = 0x1 << 0; \
536 mask = 0x1 << ((id) + 10); \
539 mask; \
683 unsigned int mask; \
686 mask
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/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/cif/
H A Dregs.h516 unsigned int mask; \
519 mask = 0x1 << 0; \
522 mask = 0x1 << (id + 10); \
525 mask; \
532 unsigned int mask; \
535 mask = 0x1 << 0; \
538 mask = 0x1 << (id + 10); \
541 mask; \
685 unsigned int mask; \
688 mask
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/device/soc/hisilicon/common/platform/mipi_csi/
H A Dmipi_rx_hi2121.h106 void MipiRxDrvSetLvdsCtrlIntMask(uint8_t devno, unsigned int mask);
107 void MipiRxDrvSetMipiCtrlIntMask(uint8_t devno, unsigned int mask);
108 void MipiRxDrvSetMipiPkt1IntMask(uint8_t devno, unsigned int mask);
109 void MipiRxDrvSetMipiPkt2IntMask(uint8_t devno, unsigned int mask);
110 void MipiRxDrvSetMipiFrameIntMask(uint8_t devno, unsigned int mask);
111 void MipiRxDrvSetAlignIntMask(uint8_t devno, unsigned int mask);
/device/soc/rockchip/common/sdk_linux/include/linux/
H A Ddmaengine.h68 /* last transaction type for creation of the capabilities mask */
482 * @src_addr_widths: bit mask of src addr widths the channel supports.
484 * a width of 4 the mask should have BIT(4) set.
485 * @dst_addr_widths: bit mask of dst addr widths the channel supports
486 * @directions: bit mask of slave directions the channel supports.
532 * satisfies the given capability mask. It returns 'true' to indicate that the
785 * @src_addr_widths: bit mask of src addr widths the device supports
787 * a width of 4 the mask should have BIT(4) set.
788 * @dst_addr_widths: bit mask of dst addr widths the device supports
789 * @directions: bit mask o
1229 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; dmaf_p_disabled_continue() local
1475 __dma_request_channel(const dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param, struct device_node *np) __dma_request_channel() argument
1484 dma_request_chan_by_mask(const dma_cap_mask_t *mask) dma_request_chan_by_mask() argument
1553 dma_request_slave_channel_compat(const dma_cap_mask_t mask, dma_filter_fn fn, void *fn_param, struct device *dev, const char *name) dma_request_slave_channel_compat() argument
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/device/soc/rockchip/rk3588/kernel/drivers/gpio/
H A Dgpio-rockchip.c396 u32 mask = BIT(d->hwirq); in rockchip_irq_set_type() local
423 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
428 bank->toggle_edge_mode |= mask; in rockchip_irq_set_type()
429 level |= mask; in rockchip_irq_set_type()
436 if (data & mask) in rockchip_irq_set_type()
437 polarity &= ~mask; in rockchip_irq_set_type()
439 polarity |= mask; in rockchip_irq_set_type()
443 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
444 level |= mask; in rockchip_irq_set_type()
445 polarity |= mask; in rockchip_irq_set_type()
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