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Searched refs:kbase_reg_read (Results 1 - 25 of 74) sorted by relevance

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/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_gpuprops_backend.c39 registers.gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID)); in kbase_backend_gpuprops_get()
41 registers.l2_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_FEATURES)); in kbase_backend_gpuprops_get()
43 registers.core_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(CORE_FEATURES)); in kbase_backend_gpuprops_get()
47 registers.tiler_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(TILER_FEATURES)); in kbase_backend_gpuprops_get()
48 registers.mem_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(MEM_FEATURES)); in kbase_backend_gpuprops_get()
49 registers.mmu_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(MMU_FEATURES)); in kbase_backend_gpuprops_get()
50 registers.as_present = kbase_reg_read(kbdev, GPU_CONTROL_REG(AS_PRESENT)); in kbase_backend_gpuprops_get()
52 registers.js_present = kbase_reg_read(kbdev, GPU_CONTROL_REG(JS_PRESENT)); in kbase_backend_gpuprops_get()
59 registers.js_features[i] = kbase_reg_read(kbdev, GPU_CONTROL_REG(JS_FEATURES_REG(i))); in kbase_backend_gpuprops_get()
65 registers.texture_features[i] = kbase_reg_read(kbde in kbase_backend_gpuprops_get()
[all...]
H A Dmali_kbase_time.c36 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI)); in kbase_backend_get_gpu_time_norequest()
37 *cycle_counter = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_LO)); in kbase_backend_get_gpu_time_norequest()
38 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI)); in kbase_backend_get_gpu_time_norequest()
46 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI)); in kbase_backend_get_gpu_time_norequest()
47 *system_time = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_LO)); in kbase_backend_get_gpu_time_norequest()
48 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI)); in kbase_backend_get_gpu_time_norequest()
H A Dmali_kbase_jm_hw.c354 completion_code = kbase_reg_read(kbdev, JOB_SLOT_REG(i, JS_STATUS)); in kbase_job_done()
363 job_tail = (u64)kbase_reg_read(kbdev, JOB_SLOT_REG(i, JS_TAIL_LO)) | in kbase_job_done()
364 ((u64)kbase_reg_read(kbdev, JOB_SLOT_REG(i, JS_TAIL_HI)) << BASE_MEM_FLAGS_NR_HI_BITS); in kbase_job_done()
389 active = kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_JS_STATE)); in kbase_job_done()
432 u32 rawstat = kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_RAWSTAT)); in kbase_job_done()
472 done = kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_RAWSTAT)); in kbase_job_done()
505 job_in_head_before = ((u64)kbase_reg_read(kbdev, JOB_SLOT_REG(js, JS_HEAD_LO))) | in kbasep_job_slot_soft_or_hard_stop_do_action()
506 (((u64)kbase_reg_read(kbdev, JOB_SLOT_REG(js, JS_HEAD_HI))) << BASE_MEM_FLAGS_NR_HI_BITS); in kbasep_job_slot_soft_or_hard_stop_do_action()
507 status_reg_before = kbase_reg_read(kbdev, JOB_SLOT_REG(js, JS_STATUS)); in kbasep_job_slot_soft_or_hard_stop_do_action()
542 status_reg_after = kbase_reg_read(kbde in kbasep_job_slot_soft_or_hard_stop_do_action()
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_gpuprops_backend.c39 registers.gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID)); in kbase_backend_gpuprops_get()
41 registers.l2_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
46 registers.core_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
54 kbase_reg_read(kbdev, GPU_CONTROL_REG(CORE_FEATURES)); in kbase_backend_gpuprops_get()
56 registers.tiler_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
58 registers.mem_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
60 registers.mmu_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
62 registers.as_present = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
65 registers.js_present = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
73 registers.js_features[i] = kbase_reg_read(kbde in kbase_backend_gpuprops_get()
[all...]
H A Dmali_kbase_time.c41 hi1 = kbase_reg_read(kbdev, in kbase_backend_get_gpu_time_norequest()
43 *system_time = kbase_reg_read(kbdev, in kbase_backend_get_gpu_time_norequest()
45 hi2 = kbase_reg_read(kbdev, in kbase_backend_get_gpu_time_norequest()
78 if ((kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_STATUS)) & in timedwait_cycle_count_active()
158 hi1 = kbase_reg_read(kbdev, in kbase_backend_get_cycle_cnt()
160 lo = kbase_reg_read(kbdev, in kbase_backend_get_cycle_cnt()
162 hi2 = kbase_reg_read(kbdev, in kbase_backend_get_cycle_cnt()
H A Dmali_kbase_jm_hw.c424 completion_code = kbase_reg_read(kbdev, in kbase_job_done()
439 job_tail = (u64)kbase_reg_read(kbdev, in kbase_job_done()
441 ((u64)kbase_reg_read(kbdev, in kbase_job_done()
474 active = kbase_reg_read(kbdev, in kbase_job_done()
519 u32 rawstat = kbase_reg_read(kbdev, in kbase_job_done()
570 done = kbase_reg_read(kbdev, in kbase_job_done()
608 job_in_head_before = ((u64) kbase_reg_read(kbdev, in kbasep_job_slot_soft_or_hard_stop_do_action()
610 | (((u64) kbase_reg_read(kbdev, in kbasep_job_slot_soft_or_hard_stop_do_action()
613 status_reg_before = kbase_reg_read(kbdev, JOB_SLOT_REG(js, JS_STATUS)); in kbasep_job_slot_soft_or_hard_stop_do_action()
650 status_reg_after = kbase_reg_read(kbde in kbasep_job_slot_soft_or_hard_stop_do_action()
[all...]
H A Dmali_kbase_model_linux.c50 while ((val = kbase_reg_read(kbdev, in serve_job_irq()
78 while ((val = kbase_reg_read(kbdev, in serve_gpu_irq()
98 while ((val = kbase_reg_read(kbdev, in serve_mmu_irq()
153 u32 kbase_reg_read(struct kbase_device *kbdev, u32 offset) in kbase_reg_read() function
165 KBASE_EXPORT_TEST_API(kbase_reg_read); variable
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_gpuprops_backend.c35 regdump->gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID), NULL); in kbase_backend_gpuprops_get()
37 regdump->l2_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
39 regdump->suspend_size = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
41 regdump->tiler_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
43 regdump->mem_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
45 regdump->mmu_features = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
47 regdump->as_present = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
49 regdump->js_present = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
53 regdump->js_features[i] = kbase_reg_read(kbdev, in kbase_backend_gpuprops_get()
57 regdump->texture_features[i] = kbase_reg_read(kbde in kbase_backend_gpuprops_get()
[all...]
H A Dmali_kbase_time.c33 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), in kbase_backend_get_gpu_time()
35 *cycle_counter = kbase_reg_read(kbdev, in kbase_backend_get_gpu_time()
37 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), in kbase_backend_get_gpu_time()
45 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI), in kbase_backend_get_gpu_time()
47 *system_time = kbase_reg_read(kbdev, in kbase_backend_get_gpu_time()
49 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI), in kbase_backend_get_gpu_time()
87 new_count = kbase_reg_read(kctx->kbdev, in kbase_wait_write_flush()
H A Dmali_kbase_mmu_hw_direct.c69 u32 val = kbase_reg_read(kbdev, MMU_AS_REG(as_nr, AS_STATUS), kctx); in wait_ready()
74 val = kbase_reg_read(kbdev, MMU_AS_REG(as_nr, AS_STATUS), NULL); in wait_ready()
83 kbase_reg_read(kbdev, MMU_AS_REG(as_nr, AS_STATUS), kctx); in wait_ready()
114 protected_debug_mode = kbase_reg_read(kbdev, in validate_protected_page_fault()
145 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
176 as->fault_addr = kbase_reg_read(kbdev, in kbase_mmu_interrupt()
181 as->fault_addr |= kbase_reg_read(kbdev, in kbase_mmu_interrupt()
199 as->fault_status = kbase_reg_read(kbdev, in kbase_mmu_interrupt()
210 as->fault_extra_addr = kbase_reg_read(kbdev, in kbase_mmu_interrupt()
214 as->fault_extra_addr |= kbase_reg_read(kbde in kbase_mmu_interrupt()
[all...]
H A Dmali_kbase_jm_hw.c50 return !kbase_reg_read(kbdev, JOB_SLOT_REG(js, JS_COMMAND_NEXT), kctx); in kbasep_jm_is_js_free()
271 completion_code = kbase_reg_read(kbdev, in kbase_job_done()
289 job_tail = (u64)kbase_reg_read(kbdev, in kbase_job_done()
292 ((u64)kbase_reg_read(kbdev, in kbase_job_done()
318 active = kbase_reg_read(kbdev, in kbase_job_done()
364 u32 rawstat = kbase_reg_read(kbdev, in kbase_job_done()
414 done = kbase_reg_read(kbdev, in kbase_job_done()
421 kbase_reg_read(kbdev, in kbase_job_done()
496 job_in_head_before = ((u64) kbase_reg_read(kbdev, in kbasep_job_slot_soft_or_hard_stop_do_action()
498 | (((u64) kbase_reg_read(kbde in kbasep_job_slot_soft_or_hard_stop_do_action()
[all...]
H A Dmali_kbase_pm_driver.c159 raw = kbase_reg_read(kbdev, in mali_cci_flush_l2()
166 raw = kbase_reg_read(kbdev, in mali_cci_flush_l2()
309 lo = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg), NULL); in kbase_pm_get_state()
310 hi = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg + 4), NULL); in kbase_pm_get_state()
957 kbase_reg_read(kbdev, in kbase_pm_check_transitions_sync()
959 kbase_reg_read(kbdev, in kbase_pm_check_transitions_sync()
963 kbase_reg_read(kbdev, in kbase_pm_check_transitions_sync()
965 kbase_reg_read(kbdev, in kbase_pm_check_transitions_sync()
968 kbase_reg_read(kbdev, in kbase_pm_check_transitions_sync()
970 kbase_reg_read(kbde in kbase_pm_check_transitions_sync()
[all...]
H A Dmali_kbase_device_hw.c175 u32 kbase_reg_read(struct kbase_device *kbdev, u16 offset, in kbase_reg_read() function
197 KBASE_EXPORT_TEST_API(kbase_reg_read); variable
214 status = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTSTATUS), NULL); in kbase_report_gpu_fault()
215 address = (u64) kbase_reg_read(kbdev, in kbase_report_gpu_fault()
217 address |= kbase_reg_read(kbdev, in kbase_report_gpu_fault()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_gpuprops_backend.c30 regdump->gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID), NULL); in kbase_backend_gpuprops_get()
32 regdump->l2_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_FEATURES), NULL); in kbase_backend_gpuprops_get()
33 regdump->suspend_size = kbase_reg_read(kbdev, GPU_CONTROL_REG(SUSPEND_SIZE), NULL); in kbase_backend_gpuprops_get()
34 regdump->tiler_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(TILER_FEATURES), NULL); in kbase_backend_gpuprops_get()
35 regdump->mem_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(MEM_FEATURES), NULL); in kbase_backend_gpuprops_get()
36 regdump->mmu_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(MMU_FEATURES), NULL); in kbase_backend_gpuprops_get()
37 regdump->as_present = kbase_reg_read(kbdev, GPU_CONTROL_REG(AS_PRESENT), NULL); in kbase_backend_gpuprops_get()
38 regdump->js_present = kbase_reg_read(kbdev, GPU_CONTROL_REG(JS_PRESENT), NULL); in kbase_backend_gpuprops_get()
41 regdump->js_features[i] = kbase_reg_read(kbdev, GPU_CONTROL_REG(JS_FEATURES_REG(i)), NULL); in kbase_backend_gpuprops_get()
45 regdump->texture_features[i] = kbase_reg_read(kbde in kbase_backend_gpuprops_get()
[all...]
H A Dmali_kbase_time.c33 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), NULL); in kbase_backend_get_gpu_time()
34 *cycle_counter = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL); in kbase_backend_get_gpu_time()
35 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), NULL); in kbase_backend_get_gpu_time()
42 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI), NULL); in kbase_backend_get_gpu_time()
43 *system_time = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_LO), NULL); in kbase_backend_get_gpu_time()
44 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI), NULL); in kbase_backend_get_gpu_time()
81 new_count = kbase_reg_read(kctx->kbdev, GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL); in kbase_wait_write_flush()
H A Dmali_kbase_mmu_hw_direct.c66 u32 val = kbase_reg_read(kbdev, MMU_AS_REG(as_nr, AS_STATUS), kctx); in wait_ready()
71 val = kbase_reg_read(kbdev, MMU_AS_REG(as_nr, AS_STATUS), NULL); in wait_ready()
81 kbase_reg_read(kbdev, MMU_AS_REG(as_nr, AS_STATUS), kctx); in wait_ready()
112 protected_debug_mode = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_STATUS), kctx) & GPU_DBGEN; in validate_protected_page_fault()
141 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
171 as->fault_addr = kbase_reg_read(kbdev, MMU_AS_REG(as_no, AS_FAULTADDRESS_HI), kctx); in kbase_mmu_interrupt()
173 as->fault_addr |= kbase_reg_read(kbdev, MMU_AS_REG(as_no, AS_FAULTADDRESS_LO), kctx); in kbase_mmu_interrupt()
187 as->fault_status = kbase_reg_read(kbdev, MMU_AS_REG(as_no, AS_FAULTSTATUS), kctx); in kbase_mmu_interrupt()
193 as->fault_extra_addr = kbase_reg_read(kbdev, MMU_AS_REG(as_no, AS_FAULTEXTRA_HI), kctx); in kbase_mmu_interrupt()
195 as->fault_extra_addr |= kbase_reg_read(kbde in kbase_mmu_interrupt()
[all...]
H A Dmali_kbase_jm_hw.c46 return !kbase_reg_read(kbdev, JOB_SLOT_REG(js, JS_COMMAND_NEXT), kctx); in kbasep_jm_is_js_free()
241 completion_code = kbase_reg_read(kbdev, JOB_SLOT_REG(i, JS_STATUS), NULL); in kbase_job_done()
254 job_tail = (u64)kbase_reg_read(kbdev, JOB_SLOT_REG(i, JS_TAIL_LO), NULL) | in kbase_job_done()
255 ((u64)kbase_reg_read(kbdev, JOB_SLOT_REG(i, JS_TAIL_HI), NULL) << 0x20); in kbase_job_done()
273 active = kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_JS_STATE), NULL); in kbase_job_done()
315 u32 rawstat = kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_RAWSTAT), NULL); in kbase_job_done()
355 done = kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_RAWSTAT), NULL); in kbase_job_done()
360 if (((active >> i) & 1) && (kbase_reg_read(kbdev, JOB_SLOT_REG(i, JS_STATUS), NULL)) == 0) { in kbase_job_done()
429 job_in_head_before = ((u64)kbase_reg_read(kbdev, JOB_SLOT_REG(js, JS_HEAD_LO), NULL)) | in kbasep_job_slot_soft_or_hard_stop_do_action()
430 (((u64)kbase_reg_read(kbde in kbasep_job_slot_soft_or_hard_stop_do_action()
[all...]
H A Dmali_kbase_pm_driver.c149 raw = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT), NULL); in mali_cci_flush_l2()
154 raw = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT), NULL); in mali_cci_flush_l2()
289 lo = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg), NULL); in kbase_pm_get_state()
290 hi = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg + 4), NULL); in kbase_pm_get_state()
871 dev_err(kbdev->dev, "\tShader=%08x%08x\n", kbase_reg_read(kbdev, GPU_CONTROL_REG(SHADER_READY_HI), NULL), in kbase_pm_check_transitions_sync()
872 kbase_reg_read(kbdev, GPU_CONTROL_REG(SHADER_READY_LO), NULL)); in kbase_pm_check_transitions_sync()
873 dev_err(kbdev->dev, "\tTiler =%08x%08x\n", kbase_reg_read(kbdev, GPU_CONTROL_REG(TILER_READY_HI), NULL), in kbase_pm_check_transitions_sync()
874 kbase_reg_read(kbdev, GPU_CONTROL_REG(TILER_READY_LO), NULL)); in kbase_pm_check_transitions_sync()
875 dev_err(kbdev->dev, "\tL2 =%08x%08x\n", kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_READY_HI), NULL), in kbase_pm_check_transitions_sync()
876 kbase_reg_read(kbde in kbase_pm_check_transitions_sync()
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/
H A Dmali_kbase_csf_reset_gpu.c240 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)), in kbase_csf_debug_dump_registers()
241 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_STATUS)), in kbase_csf_debug_dump_registers()
242 kbase_reg_read(kbdev, GPU_CONTROL_REG(MCU_STATUS))); in kbase_csf_debug_dump_registers()
244 kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_RAWSTAT)), in kbase_csf_debug_dump_registers()
245 kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_RAWSTAT)), in kbase_csf_debug_dump_registers()
246 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTSTATUS))); in kbase_csf_debug_dump_registers()
248 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)), in kbase_csf_debug_dump_registers()
249 kbase_reg_read(kbdev, JOB_CONTROL_REG(JOB_IRQ_MASK)), in kbase_csf_debug_dump_registers()
250 kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK))); in kbase_csf_debug_dump_registers()
252 kbase_reg_read(kbde in kbase_csf_debug_dump_registers()
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/device/backend/
H A Dmali_kbase_device_hw_jm.c41 u32 status = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTSTATUS)); in kbase_report_gpu_fault()
42 u64 address = (u64) kbase_reg_read(kbdev, in kbase_report_gpu_fault()
45 address |= kbase_reg_read(kbdev, in kbase_report_gpu_fault()
118 u32 kbase_reg_read(struct kbase_device *kbdev, u32 offset) in kbase_reg_read() function
136 KBASE_EXPORT_TEST_API(kbase_reg_read); variable
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/mmu/backend/
H A Dmali_kbase_mmu_jm.c289 protected_debug_mode = kbase_reg_read(kbdev, in validate_protected_page_fault()
323 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
356 fault->addr = kbase_reg_read(kbdev, MMU_AS_REG(as_no, in kbase_mmu_interrupt()
359 fault->addr |= kbase_reg_read(kbdev, MMU_AS_REG(as_no, in kbase_mmu_interrupt()
373 fault->status = kbase_reg_read(kbdev, MMU_AS_REG(as_no, in kbase_mmu_interrupt()
375 fault->extra_addr = kbase_reg_read(kbdev, in kbase_mmu_interrupt()
378 fault->extra_addr |= kbase_reg_read(kbdev, in kbase_mmu_interrupt()
407 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/mmu/backend/
H A Dmali_kbase_mmu_jm.c256 protected_debug_mode = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_STATUS)) & GPU_DBGEN; in validate_protected_page_fault()
289 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
323 fault->addr = kbase_reg_read(kbdev, MMU_AS_REG(as_no, AS_FAULTADDRESS_HI)); in kbase_mmu_interrupt()
325 fault->addr |= kbase_reg_read(kbdev, MMU_AS_REG(as_no, AS_FAULTADDRESS_LO)); in kbase_mmu_interrupt()
338 fault->status = kbase_reg_read(kbdev, MMU_AS_REG(as_no, AS_FAULTSTATUS)); in kbase_mmu_interrupt()
341 fault->extra_addr = kbase_reg_read(kbdev, MMU_AS_REG(as_no, AS_FAULTEXTRA_HI)); in kbase_mmu_interrupt()
343 fault->extra_addr |= kbase_reg_read(kbdev, MMU_AS_REG(as_no, AS_FAULTEXTRA_LO)); in kbase_mmu_interrupt()
371 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/device/
H A Dmali_kbase_device_hw.c35 val = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID)); in kbase_is_gpu_removed()
51 !(kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)) & in busy_wait_cache_clean_irq()
92 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_gpu_cache_flush_and_busy_wait()
150 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_gpu_start_cache_clean_nolock()
196 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_clean_caches_done()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/device/
H A Dmali_kbase_device_hw.c50 u32 kbase_reg_read(struct kbase_device *kbdev, u32 offset) in kbase_reg_read() function
69 KBASE_EXPORT_TEST_API(kbase_reg_read); variable
75 val = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID)); in kbase_is_gpu_removed()
98 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_gpu_start_cache_clean_nolock()
139 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_clean_caches_done()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/device/backend/
H A Dmali_kbase_device_hw_jm.c43 u32 status = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTSTATUS)); in kbase_report_gpu_fault()
44 u64 address = (u64)kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTADDRESS_HI)) << 32; in kbase_report_gpu_fault()
46 address |= kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTADDRESS_LO)); in kbase_report_gpu_fault()

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