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Searched refs:hi_reg_write16 (Results 1 - 22 of 22) sorted by relevance

/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/tsensor/
H A Dhi_tsensor_pm.c78 hi_reg_write16((TSENSOR_BASE_ADDRESS + TSENSOR_TRIM_CTRL), g_lp_regs_save.trim_ctrl); in hi_tsensor_lp_restore()
79 hi_reg_write16((TSENSOR_BASE_ADDRESS + TSENSOR_TEMP_HIGH_LIMIT), g_lp_regs_save.high_limit); in hi_tsensor_lp_restore()
80 hi_reg_write16((TSENSOR_BASE_ADDRESS + TSENSOR_TEMP_LOW_LIMIT), g_lp_regs_save.low_limit); in hi_tsensor_lp_restore()
81 hi_reg_write16((TSENSOR_BASE_ADDRESS + TSENSOR_TEMP_OVER_LIMIT), g_lp_regs_save.over_limit); in hi_tsensor_lp_restore()
82 hi_reg_write16((TSENSOR_BASE_ADDRESS + TSENSOR_TEMP_PD_LIMIT), g_lp_regs_save.pd_limit); in hi_tsensor_lp_restore()
84 hi_reg_write16((TSENSOR_BASE_ADDRESS + TSENSOR_TEMP_INT_EN), g_lp_regs_save.int_en); in hi_tsensor_lp_restore()
85 hi_reg_write16((TSENSOR_BASE_ADDRESS + TSENSOR_TEMP_INT_CLR), g_lp_regs_save.int_clr); in hi_tsensor_lp_restore()
95 hi_reg_write16(W_CTL_TSENSOR_DIV_REG, g_lp_regs_save.clk_div); in hi_tsensor_lp_restore()
96 hi_reg_write16((TSENSOR_BASE_ADDRESS + TSENSOR_CTRL), g_lp_regs_save.ctrl); in hi_tsensor_lp_restore()
97 hi_reg_write16((TSENSOR_BASE_ADDRES in hi_tsensor_lp_restore()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/src/
H A Dapp_main.c184 hi_reg_write16(CLDO_CTL_CLKEN_REG, reg_val); /* disable clken0 clk gate */ in peripheral_close_clken()
190 hi_reg_write16(CLDO_CTL_CLKEN1_REG, reg_val); /* disable clken1 clk gate */ in peripheral_close_clken()
195 hi_reg_write16(CLDO_CTL_CLKEN2_REG, reg_val); /* disable clken2 clk gate */ in peripheral_close_clken()
202 hi_reg_write16(W_CTL_UART_MAC80M_CLKEN_REG, reg_val); /* disable uart_mac80m clk gate */ in peripheral_close_clken()
203 hi_reg_write16(PMU_CMU_CTL_CLK_960M_GT_REG, 0x1); /* disable 960m clk gate */ in peripheral_close_clken()
351 hi_reg_write16(iocfg_reg_addr(HI_IO_NAME_GPIO_6), IOCFG_LOWPOWER_CFG_VAL); in config_before_sleep()
352 hi_reg_write16(iocfg_reg_addr(HI_IO_NAME_GPIO_8), IOCFG_LOWPOWER_CFG_VAL); in config_before_sleep()
353 hi_reg_write16(iocfg_reg_addr(HI_IO_NAME_GPIO_10), IOCFG_LOWPOWER_CFG_VAL); in config_before_sleep()
354 hi_reg_write16(iocfg_reg_addr(HI_IO_NAME_GPIO_11), IOCFG_LOWPOWER_CFG_VAL); in config_before_sleep()
355 hi_reg_write16(iocfg_reg_add in config_before_sleep()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/app/wifiiot_app/src/
H A Dapp_main.c169 hi_reg_write16(CLDO_CTL_CLKEN_REG, reg_val); /* disable clken0 clk gate */ in peripheral_close_clken()
175 hi_reg_write16(CLDO_CTL_CLKEN1_REG, reg_val); /* disable clken1 clk gate */ in peripheral_close_clken()
180 hi_reg_write16(CLDO_CTL_CLKEN2_REG, reg_val); /* disable clken2 clk gate */ in peripheral_close_clken()
187 hi_reg_write16(W_CTL_UART_MAC80M_CLKEN_REG, reg_val); /* disable uart_mac80m clk gate */ in peripheral_close_clken()
188 hi_reg_write16(PMU_CMU_CTL_CLK_960M_GT_REG, 0x1); /* disable 960m clk gate */ in peripheral_close_clken()
325 hi_reg_write16(iocfg_reg_addr(HI_IO_NAME_GPIO_6), IOCFG_LOWPOWER_CFG_VAL); in config_before_sleep()
326 hi_reg_write16(iocfg_reg_addr(HI_IO_NAME_GPIO_8), IOCFG_LOWPOWER_CFG_VAL); in config_before_sleep()
327 hi_reg_write16(iocfg_reg_addr(HI_IO_NAME_GPIO_10), IOCFG_LOWPOWER_CFG_VAL); in config_before_sleep()
328 hi_reg_write16(iocfg_reg_addr(HI_IO_NAME_GPIO_11), IOCFG_LOWPOWER_CFG_VAL); in config_before_sleep()
329 hi_reg_write16(iocfg_reg_add in config_before_sleep()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/uart/
H A Dhi_uart.c250 hi_reg_write16(W_CTL_UART_MAC80M_CLKEN_REG, reg_val); /* enable uart2 clk */ in hi_uart_init()
398 hi_reg_write16(W_CTL_UART_MAC80M_CLKEN_REG, reg_val); /* disable uart2 clk */ in hi_uart_deinit()
469 hi_reg_write16(W_CTL_UART_MAC80M_CLKEN_REG, temp); /* enable uart2 clk */ in hi_uart_lp_restore()
474 hi_reg_write16((phys_base + UART_CR), 0); in hi_uart_lp_restore()
476 hi_reg_write16((phys_base + UART_LCR_H), 0); in hi_uart_lp_restore()
478 hi_reg_write16((phys_base + UART_IBRD), g_uart_regs_save[port_num].ibrd); in hi_uart_lp_restore()
479 hi_reg_write16((phys_base + UART_FBRD), g_uart_regs_save[port_num].fbrd); in hi_uart_lp_restore()
481 hi_reg_write16((phys_base + UART_LCR_H), g_uart_regs_save[port_num].lcr_h); in hi_uart_lp_restore()
483 hi_reg_write16(phys_base + UART_IFLS, g_uart_regs_save[port_num].ifls); /* default val: 0x10A */ in hi_uart_lp_restore()
485 hi_reg_write16((phys_bas in hi_uart_lp_restore()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/init/
H A Dapp_io_init.c23 hi_reg_write16(DIAG_CTL_DIAG_MUX, 0x2); in app_io_set_gpio2_clkout_enable()
24 hi_reg_write16(DIAG_CTL_CLOCK_TEST_DIV, 0x0); in app_io_set_gpio2_clkout_enable()
25 hi_reg_write16(DIAG_CTL_CLOCK_TEST_EN, 0x3FFF); in app_io_set_gpio2_clkout_enable()
26 hi_reg_write16(DIAG_CTL_CLOCK_TEST_SEL, 0x1); in app_io_set_gpio2_clkout_enable()
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/spi/
H A Dspi.c136 hi_reg_write16(ctrl->reg_base + REG_SPI_CR1, reg_val); in spi_disable()
145 hi_reg_write16(ctrl->reg_base + REG_SPI_CR1, reg_val); in spi_enable()
163 hi_reg_write16(CLDO_CTL_SOFT_RESET_REG, reg_val); in spi_reset()
165 hi_reg_write16(CLDO_CTL_SOFT_RESET_REG, reg_val); in spi_reset()
176 hi_reg_write16(spi_hw_ctrl->reg_base + REG_SPI_CR0, inner_cfg.cr0); in spi_config()
177 hi_reg_write16(spi_hw_ctrl->reg_base + REG_SPI_CR1, inner_cfg.cr1); in spi_config()
178 hi_reg_write16(spi_hw_ctrl->reg_base + REG_SPI_CPSR, inner_cfg.cpsdvsr); in spi_config()
194 hi_reg_write16(spi_hw_ctrl->reg_base + REG_SPI_TXFIFOCR, reg_val); in spi_set_fifo_line()
198 hi_reg_write16(spi_hw_ctrl->reg_base + REG_SPI_RXFIFOCR, reg_val); in spi_set_fifo_line()
211 hi_reg_write16(spi_hw_ctr in spi_set_dma_fifo_line()
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H A Dhi_spi.c53 hi_reg_write16(W_CTL_W_TCXO_SEL_REG, 1); in spi_get_clk()
260 hi_reg_write16(g_spi_ctrl[id]->reg_base + REG_SPI_CR1, reg_val); in hi_spi_set_loop_back_mode()
501 hi_reg_write16(CLDO_CTL_CLKEN_REG, reg_val); /* enable spix clk bus */ in spi_ctrl_init()
605 hi_reg_write16(CLDO_CTL_CLKEN_REG, reg_val); /* disable spix clk bus */ in hi_spi_deinit()
/device/soc/hisilicon/hi3861v100/sdk_liteos/components/at/src/
H A Dat_printf.c34 hi_reg_write16(g_at_uart_baseaddr + UART_DR, (hi_uchar)c); in serial_putc_at()
87 hi_reg_write16(g_at_uart_baseaddr + UART_DR, (hi_uchar)c); in serial_putc_crashinfo()
93 hi_reg_write16(g_sysinfo_uart_baseaddr + UART_DR, (hi_uchar)c); in serial_putc_crashinfo()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/gpio/
H A Dhi_flashboot_gpio.c70 hi_reg_write16((HI_GPIO_REG_BASE + GPIO_SWPORT_DR), reg_val); in hi_gpio_set_output_val()
97 hi_reg_write16((HI_GPIO_REG_BASE + GPIO_SWPORT_DDR), dir_val); in hi_gpio_set_dir()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/upg/
H A Dboot_start.c83 hi_reg_write16(CLDO_CTL_GEN_REG0, reg_val); in set_running_kernel_flag()
85 hi_reg_write16(CLDO_CTL_GEN_REG0, reg_val); in set_running_kernel_flag()
H A Dboot_upg_check_secure.c64 hi_reg_write16(DIAG_CTL_GP_REG0_REG, (rsa_key_addr & MASK_U16)); in boot_upg_save_rsa_key_pos()
65 hi_reg_write16(DIAG_CTL_GP_REG1_REG, (rsa_key_addr >> BIT_U16)); in boot_upg_save_rsa_key_pos()
74 hi_reg_write16(DIAG_CTL_GP_REG2_REG, (ecc_key_addr & MASK_U16)); in boot_upg_save_ecc_key_pos()
75 hi_reg_write16(DIAG_CTL_GP_REG3_REG, (ecc_key_addr >> BIT_U16)); in boot_upg_save_ecc_key_pos()
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/pwm/
H A Dhi_pwm.c74 hi_reg_write16(CLDO_CTL_CLKEN1_REG, reg_val); /* enable pwmx clk bus */ in hi_pwm_init()
97 hi_reg_write16(CLDO_CTL_CLKEN1_REG, reg_val); /* disable pwmx clk bus */ in pwm_deinit_clken()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/lsadc/
H A Dadc_drv.c56 hi_reg_write16(LS_ADC_CLK_DIV1_REG, reg_val); in get_ref_voltage()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/drivers/lsadc/
H A Dadc_drv.c56 hi_reg_write16(LS_ADC_CLK_DIV1_REG, reg_val); in get_ref_voltage()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/flash/
H A Dhi_flashboot_flash.c95 hi_reg_write16(PMU_CMU_CTL_CMU_CLK_SEL_REG, reg_val); /* Configuring Driver Capabilities */ in sfc_config_update_freq()
111 hi_reg_write16(PMU_CMU_CTL_CMU_CLK_SEL_REG, reg_val); in sfc_config_update_freq()
289 hi_reg_write16(PMU_CMU_CTL_FLASHLDO_CFG_1_REG, reg_val); in flash_clk_config()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/drivers/flash/
H A Dhi_loaderboot_flash.c95 hi_reg_write16(PMU_CMU_CTL_CMU_CLK_SEL_REG, reg_val); in sfc_config_update_freq()
112 hi_reg_write16(PMU_CMU_CTL_CMU_CLK_SEL_REG, reg_val); in sfc_config_update_freq()
237 hi_reg_write16(PMU_CMU_CTL_FLASHLDO_CFG_1_REG, reg_val); in flash_clk_config()
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/adc/
H A Dhi_adc.c71 hi_reg_write16(LS_ADC_CLK_DIV1_REG, reg_val); in hi_adc_read()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/include/
H A Dhi_boot_rom.h45 #define hi_reg_write16(addr, val) (*(volatile hi_u16*)(uintptr_t)(addr) = (val)) macro
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/i2c/
H A Di2c.c788 hi_reg_write16(CLDO_CTL_CLKEN_REG, reg_val); /* enable i2cx clk bus */ in hi_i2c_init()
828 hi_reg_write16(CLDO_CTL_CLKEN_REG, reg_val); /* disable i2cx clk bus */ in hi_i2c_deinit()
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/include/
H A Dhi_types_base.h478 #define hi_reg_write16(addr, val) (*(volatile unsigned short *)(uintptr_t)(addr) = (val)) macro
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi_types_base.h477 #define hi_reg_write16(addr, val) (*(volatile unsigned short *)(uintptr_t)(addr) = (val)) macro
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/include/
H A Dhi_boot_rom.h45 #define hi_reg_write16(addr, val) (*(volatile hi_u16*)(uintptr_t)(addr) = (val)) macro

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