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Searched refs:hi_reg_read_val32 (Results 1 - 10 of 10) sorted by relevance

/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/lsadc/
H A Dadc_drv.c22 hi_u32 reg_val = hi_reg_read_val32(REG_ADC_SR); in adc_fifo_is_empty()
34 (hi_void)hi_reg_read_val32(REG_ADC_DR); in adc_scan_stop()
72 if (hi_reg_read_val32(REG_ADC_SR) & ADC_SR_BSY) { in get_ref_voltage()
79 data = (hi_u16)hi_reg_read_val32(REG_ADC_DR); in get_ref_voltage()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/drivers/lsadc/
H A Dadc_drv.c22 hi_u32 reg_val = hi_reg_read_val32(REG_ADC_SR); in adc_fifo_is_empty()
34 (hi_void)hi_reg_read_val32(REG_ADC_DR); in adc_scan_stop()
72 if (hi_reg_read_val32(REG_ADC_SR) & ADC_SR_BSY) { in get_ref_voltage()
79 data = (hi_u16)hi_reg_read_val32(REG_ADC_DR); in get_ref_voltage()
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/include/
H A Dhi_types_base.h467 #define hi_reg_read_val32(addr) (*(volatile unsigned int*)(uintptr_t)(addr)) macro
468 #define hi_reg_setbitmsk(addr, msk) ((hi_reg_read_val32(addr)) |= (msk))
469 #define hi_reg_clrbitmsk(addr, msk) ((hi_reg_read_val32(addr)) &= ~(msk))
470 #define hi_reg_clrbit(addr, pos) ((hi_reg_read_val32(addr)) &= ~((unsigned int)(1) << (pos)))
471 #define hi_reg_setbit(addr, pos) ((hi_reg_read_val32(addr)) |= ((unsigned int)(1) << (pos)))
472 #define hi_reg_clrbits(addr, pos, bits) (hi_reg_read_val32(addr) &= ~((((unsigned int)1 << (bits)) - 1) << (pos)))
474 (hi_reg_read_val32(addr) = (hi_reg_read_val32(addr) & (~((((unsigned int)1 << (bits)) - 1) << (pos)))) | \
476 #define hi_reg_getbits(addr, pos, bits) ((hi_reg_read_val32(addr) >> (pos)) & (((unsigned int)1 << (bits)) - 1))
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi_types_base.h466 #define hi_reg_read_val32(addr) (*(volatile unsigned int*)(uintptr_t)(addr)) macro
467 #define hi_reg_setbitmsk(addr, msk) ((hi_reg_read_val32(addr)) |= (msk))
468 #define hi_reg_clrbitmsk(addr, msk) ((hi_reg_read_val32(addr)) &= ~(msk))
469 #define hi_reg_clrbit(addr, pos) ((hi_reg_read_val32(addr)) &= ~((unsigned int)(1) << (pos)))
470 #define hi_reg_setbit(addr, pos) ((hi_reg_read_val32(addr)) |= ((unsigned int)(1) << (pos)))
471 #define hi_reg_clrbits(addr, pos, bits) (hi_reg_read_val32(addr) &= ~((((unsigned int)1 << (bits)) - 1) << (pos)))
472 #define hi_reg_setbits(addr, pos, bits, val) (hi_reg_read_val32(addr) = \
473 (hi_reg_read_val32(addr) & (~((((unsigned int)1 << (bits)) - 1) << (pos)))) | \
475 #define hi_reg_getbits(addr, pos, bits) ((hi_reg_read_val32(addr) >> (pos)) & (((unsigned int)1 << (bits)) - 1))
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/include/
H A Dhi_boot_rom.h57 #define hi_reg_read_val32(addr) (*(volatile hi_u32*)(uintptr_t)(addr)) macro
69 #define hi_reg_setbitmsk(addr, msk) ((hi_reg_read_val32(addr)) |= (msk))
75 #define hi_reg_clrbitmsk(addr, msk) ((hi_reg_read_val32(addr)) &= ~(msk))
81 #define hi_reg_clrbit(addr, pos) ((hi_reg_read_val32(addr)) &= ~((hi_u32)(1) << (pos)))
87 #define hi_reg_setbit(addr, pos) ((hi_reg_read_val32(addr)) |= ((hi_u32)(1) << (pos)))
93 #define hi_reg_clrbits(addr, pos, bits) (hi_reg_read_val32(addr) &= ~((((hi_u32)1 << (bits)) - 1) << (pos)))
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/uart/
H A Duart_drv.c220 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_tx_interrupt_disable()
226 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_tx_interrupt_enable()
232 hi_u32 int_clear_status = hi_reg_read_val32(udd->phys_base + UART_ICR); in uart_tx_interrupt_clear()
238 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_rx_interrupt_disable()
244 hi_u32 tx_status = hi_reg_read_val32(udd->phys_base + UART_IMSC); in uart_rx_interrupt_enable()
394 hi_u32 usr = hi_reg_read_val32(udd->phys_base + UART_FR); in uart_dma_recv_irq()
444 hi_u32 usr = hi_reg_read_val32(udd->phys_base + UART_FR); in uart_nodma_recv_irq()
458 buf[count] = (char) hi_reg_read_val32(udd->phys_base + UART_DR); in uart_nodma_recv_irq()
513 status = hi_reg_read_val32(udd->phys_base + UART_MIS); in uart_drv_irq()
647 while ((hi_reg_read_val32(ud in uart_drv_dma_start_tx_cfg()
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/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/adc/
H A Dhi_adc.c26 hi_u32 reg_val = hi_reg_read_val32(REG_ADC_SR); in check_adc_fifo_empty()
37 (hi_void)hi_reg_read_val32(REG_ADC_DR); in wait_adc_fifo_empty()
85 *data = (hi_u16)hi_reg_read_val32(REG_ADC_DR); in hi_adc_read()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/include/
H A Dhi_boot_rom.h57 #define hi_reg_read_val32(addr) (*(volatile hi_u32*)(uintptr_t)(addr)) macro
69 #define hi_reg_setbitmsk(addr, msk) ((hi_reg_read_val32(addr)) |= (msk))
75 #define hi_reg_clrbitmsk(addr, msk) ((hi_reg_read_val32(addr)) &= ~(msk))
81 #define hi_reg_clrbit(addr, pos) ((hi_reg_read_val32(addr)) &= ~((hi_u32)(1) << (pos)))
87 #define hi_reg_setbit(addr, pos) ((hi_reg_read_val32(addr)) |= ((hi_u32)(1) << (pos)))
93 #define hi_reg_clrbits(addr, pos, bits) (hi_reg_read_val32(addr) &= ~((((hi_u32)1 << (bits)) - 1) << (pos)))
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/commonboot/efuse/
H A Defuse_drv.c181 ((hi_reg_read_val32(EFUSE_STATUS) & EFUSE_READ_READY_STATUS) != EFUSE_EN_OK)) { in efuse_read_bits()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/commonboot/
H A Dboot_rom.h253 hi_reg_read_val32(SFC_REG_BASE_ADDRESS + (_reg))

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