Searched refs:divider (Results 1 - 9 of 9) sorted by relevance
| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-dclk-divider.c | 19 struct clk_divider *divider = to_clk_divider(hw); in clk_dclk_recalc_rate() local
22 val = readl(divider->reg) >> divider->shift; in clk_dclk_recalc_rate()
23 val &= div_mask(divider->width); in clk_dclk_recalc_rate()
30 struct clk_divider *divider = to_clk_divider(hw); in clk_dclk_round_rate() local
31 int div, maxdiv = div_mask(divider->width) + 1; in clk_dclk_round_rate()
33 div = DIV_ROUND_UP_ULL(divider->max_prate, rate); in clk_dclk_round_rate()
44 struct clk_divider *divider = to_clk_divider(hw); in clk_dclk_set_rate() local
49 value = divider_get_val(rate, parent_rate, divider->table, divider in clk_dclk_set_rate()
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| H A D | Makefile | 12 clk-vendor-y += clk-dclk-divider.o
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk-dclk-divider.c | 18 struct clk_divider *divider = to_clk_divider(hw); in clk_dclk_recalc_rate() local
21 val = readl(divider->reg) >> divider->shift; in clk_dclk_recalc_rate()
22 val &= div_mask(divider->width); in clk_dclk_recalc_rate()
30 struct clk_divider *divider = to_clk_divider(hw); in clk_dclk_round_rate() local
31 int div, maxdiv = div_mask(divider->width) + 1; in clk_dclk_round_rate()
33 div = DIV_ROUND_UP_ULL(divider->max_prate, rate); in clk_dclk_round_rate()
44 struct clk_divider *divider = to_clk_divider(hw); in clk_dclk_set_rate() local
49 value = divider_get_val(rate, parent_rate, divider->table, in clk_dclk_set_rate()
50 divider in clk_dclk_set_rate()
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-half-divider.c | 24 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
27 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
28 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
60 * The maximum divider we can use without overflowing in clk_half_divider_bestdiv()
89 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_round_rate() local
92 div = clk_half_divider_bestdiv(hw, rate, prate, divider->width, divider->flags); in clk_half_divider_round_rate()
99 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_set_rate() local
106 value = min_t(unsigned int, value, div_mask(divider in clk_half_divider_set_rate()
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| /device/soc/rockchip/common/sdk_linux/kernel/sched/ |
| H A D | pelt.c | 301 u32 divider = get_pelt_divider(sa); in ___update_load_avg() local
306 sa->load_avg = div_u64(load * sa->load_sum, divider); in ___update_load_avg()
307 sa->runnable_avg = div_u64(sa->runnable_sum, divider); in ___update_load_avg()
308 WRITE_ONCE(sa->util_avg, sa->util_sum / divider); in ___update_load_avg()
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| H A D | fair.c | 3220 u32 divider = get_pelt_divider(&se->avg); in reweight_entity() local
3222 se->avg.load_avg = div_u64(se_weight(se) * se->avg.load_sum, divider); in reweight_entity()
3566 u32 divider; in update_tg_cfs_util() local
3577 divider = get_pelt_divider(&cfs_rq->avg); in update_tg_cfs_util()
3581 se->avg.util_sum = se->avg.util_avg * divider; in update_tg_cfs_util()
3585 cfs_rq->avg.util_sum = cfs_rq->avg.util_avg * divider; in update_tg_cfs_util()
3591 u32 divider; in update_tg_cfs_runnable() local
3602 divider = get_pelt_divider(&cfs_rq->avg); in update_tg_cfs_runnable()
3606 se->avg.runnable_sum = se->avg.runnable_avg * divider; in update_tg_cfs_runnable()
3610 cfs_rq->avg.runnable_sum = cfs_rq->avg.runnable_avg * divider; in update_tg_cfs_runnable()
3618 u32 divider; update_tg_cfs_load() local
3782 u32 divider = get_pelt_divider(&cfs_rq->avg); update_cfs_rq_load_avg() local
3848 u32 divider = get_pelt_divider(&cfs_rq->avg); attach_entity_load_avg() local
3903 u32 divider = get_pelt_divider(&cfs_rq->avg); detach_entity_load_avg() local
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| H A D | Makefile | 12 clk-vendor-y += clk-dclk-divider.o
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| /device/soc/hisilicon/common/platform/uart/ |
| H A D | uart_pl011.c | 72 uint32_t divider; in Pl011ConfigBaudrate() local
83 divider = CONFIG_UART_CLK_INPUT / value; in Pl011ConfigBaudrate()
87 OSAL_WRITEL(divider, port->physBase + UART_IBRD); in Pl011ConfigBaudrate()
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| /device/qemu/drivers/uart/ |
| H A D | uart_pl011.c | 73 uint32_t divider; in Pl011ConfigBaudrate() local
84 divider = CONFIG_UART_CLK_INPUT / value; in Pl011ConfigBaudrate()
88 OSAL_WRITEL(divider, port->physBase + UART_IBRD); in Pl011ConfigBaudrate()
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