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Searched refs:div (Results 1 - 25 of 32) sorted by relevance

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/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-dclk-divider.c31 int div, maxdiv = div_mask(divider->width) + 1; in clk_dclk_round_rate() local
33 div = DIV_ROUND_UP_ULL(divider->max_prate, rate); in clk_dclk_round_rate()
34 if (div % div_odd) { in clk_dclk_round_rate()
35 div = __rounddown_pow_of_two(div); in clk_dclk_round_rate()
37 div = div > maxdiv ? maxdiv : div; in clk_dclk_round_rate()
38 *prate = div * rate; in clk_dclk_round_rate()
102 struct clk_divider *div in rockchip_clk_register_dclk_branch() local
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H A Dclk-pvtm.c130 u32 div, time_us; in rockchip_clock_pvtm_init_freq() local
138 div = DIV_ROUND_UP(0x3e8 * pvtm_cnt, pvtm->rate); in rockchip_clock_pvtm_init_freq()
139 if (div > pvtm->info->div_mask) { in rockchip_clock_pvtm_init_freq()
141 div = pvtm->info->div_mask; in rockchip_clock_pvtm_init_freq()
144 pr_debug("set div %d, rate %luKHZ\n", div, pvtm->rate); in rockchip_clock_pvtm_init_freq()
145 ret = regmap_write(pvtm->grf, pvtm->info->con, wr_msk_bit(div, pvtm->info->div_shift, pvtm->info->div_mask)); in rockchip_clock_pvtm_init_freq()
/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk-dclk-divider.c31 int div, maxdiv = div_mask(divider->width) + 1; in clk_dclk_round_rate() local
33 div = DIV_ROUND_UP_ULL(divider->max_prate, rate); in clk_dclk_round_rate()
34 if (div % 2) in clk_dclk_round_rate()
35 div = __rounddown_pow_of_two(div); in clk_dclk_round_rate()
36 div = div > maxdiv ? maxdiv : div; in clk_dclk_round_rate()
37 *prate = div * rate; in clk_dclk_round_rate()
109 struct clk_divider *div in rockchip_clk_register_dclk_branch() local
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H A Dclk-pvtm.c131 u32 div, time_us; in rockchip_clock_pvtm_init_freq() local
139 div = DIV_ROUND_UP(1000 * pvtm_cnt, pvtm->rate); in rockchip_clock_pvtm_init_freq()
140 if (div > pvtm->info->div_mask) { in rockchip_clock_pvtm_init_freq()
142 div = pvtm->info->div_mask; in rockchip_clock_pvtm_init_freq()
145 pr_debug("set div %d, rate %luKHZ\n", div, pvtm->rate); in rockchip_clock_pvtm_init_freq()
147 wr_msk_bit(div, pvtm->info->div_shift, in rockchip_clock_pvtm_init_freq()
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-half-divider.c90 int div; in clk_half_divider_round_rate() local
92 div = clk_half_divider_bestdiv(hw, rate, prate, divider->width, divider->flags); in clk_half_divider_round_rate()
94 return DIV_ROUND_UP_ULL(((u64)*prate * 0x2), div * 0x2 + 0x3); in clk_half_divider_round_rate()
157 struct clk_divider *div = NULL; in rockchip_clk_register_halfdiv() local
188 div = kzalloc(sizeof(*div), GFP_KERNEL); in rockchip_clk_register_halfdiv()
189 if (!div) { in rockchip_clk_register_halfdiv()
193 div->flags = div_flags; in rockchip_clk_register_halfdiv()
195 div->reg = base + div_offset; in rockchip_clk_register_halfdiv()
197 div in rockchip_clk_register_halfdiv()
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H A Dclk.c47 struct clk_divider *div = NULL; in rockchip_clk_register_branch() local
81 div = kzalloc(sizeof(*div), GFP_KERNEL); in rockchip_clk_register_branch()
82 if (!div) { in rockchip_clk_register_branch()
87 div->flags = div_flags; in rockchip_clk_register_branch()
89 div->reg = base + div_offset; in rockchip_clk_register_branch()
91 div->reg = base + muxdiv_offset; in rockchip_clk_register_branch()
93 div->shift = div_shift; in rockchip_clk_register_branch()
94 div->width = div_width; in rockchip_clk_register_branch()
95 div in rockchip_clk_register_branch()
118 struct clk_fractional_divider div; global() member
172 u32 div; rockchip_fractional_approximation() local
231 struct clk_fractional_divider *div = NULL; rockchip_clk_register_frac_branch() local
327 rockchip_clk_register_factor_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, unsigned int mult, unsigned int div, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) rockchip_clk_register_factor_branch() argument
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H A Dclk-rk3188.c236 {.val = 0, .div = 2}, {.val = 1, .div = 4}, {.val = 2, .div = 8}, {.val = 3, .div = 16}, {},
467 {.val = 0, .div = 1}, {.val = 1, .div = 2}, {.val = 2, .div = 3},
468 {.val = 3, .div = 4}, {.val = 4, .div = 8}, {},
547 {.val = 0, .div
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H A Dclk-rk3368.c159 {.val = 0, .div = 1},
160 {.val = 1, .div = 2},
161 {.val = 3, .div = 4},
H A Dclk-rk3128.c470 void rkclk_cpuclk_div_setting(int div) in rkclk_cpuclk_div_setting() argument
473 writel_relaxed((0x001f0000 | (div - 1)), rk312x_reg_base + RK2928_CLKSEL_CON(0)); in rkclk_cpuclk_div_setting()
H A Dclk-rk3288.c187 {.val = 0, .div = 1},
188 {.val = 1, .div = 2},
189 {.val = 3, .div = 4},
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c72 * We only use this clk driver calculate the div
193 unsigned int div, value; in vop2_div_get_val() local
195 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in vop2_div_get_val()
197 value = ilog2(div); in vop2_div_get_val()
206 unsigned int div; in vop2_clk_div_recalc_rate() local
208 div = 1 << vop2_clk->div_val; in vop2_clk_div_recalc_rate()
209 rate = parent_rate / div; in vop2_clk_div_recalc_rate()
224 if ((*prate >> vop2_clk->div.width) > rate) { in vop2_clk_div_round_rate()
234 *prate = rate << vop2_clk->div.width; in vop2_clk_div_round_rate()
275 vop2_clk->div in vop2_clk_register()
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H A Drockchip_drm_vop.h1236 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_clk.c83 * We only use this clk driver calculate the div
211 unsigned int div, value; in vop2_div_get_val() local
213 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in vop2_div_get_val()
215 value = ilog2(div); in vop2_div_get_val()
225 unsigned int div; in vop2_clk_div_recalc_rate() local
227 div = 1 << vop2_clk->div_val; in vop2_clk_div_recalc_rate()
228 rate = parent_rate / div; in vop2_clk_div_recalc_rate()
243 if ((*prate >> vop2_clk->div.width) > rate) in vop2_clk_div_round_rate()
251 *prate = rate << vop2_clk->div.width; in vop2_clk_div_round_rate()
291 vop2_clk->div in vop2_clk_register()
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/device/soc/rockchip/common/sdk_linux/drivers/pwm/
H A Dpwm-rockchip.c113 u64 div; in rockchip_pwm_config() local
121 div = (u64)pc->clk_rate * state->period; in rockchip_pwm_config()
122 period = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); in rockchip_pwm_config()
124 div = (u64)pc->clk_rate * state->duty_cycle; in rockchip_pwm_config()
125 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); in rockchip_pwm_config()
/device/soc/rockchip/common/sdk_linux/include/linux/
H A Dclk-provider.h519 unsigned int div; member
529 * @table: array of value/divider pairs, last entry should have div = 0
678 * @table: array of divider/value pairs ending with a div set to 0
696 * @table: array of divider/value pairs ending with a div set to 0
714 * @table: array of divider/value pairs ending with a div set to 0
815 * @div: divider
818 * parent clock rate divided by div and multiplied by mult.
825 unsigned int div; member
832 unsigned long flags, unsigned int mult, unsigned int div);
835 unsigned long flags, unsigned int mult, unsigned int div);
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/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/
H A Dstdlib.h521 div_t div (int, int);
/device/soc/rockchip/common/vendor/drivers/gpio/
H A Dgpio-rockchip.c196 u64 div; in rockchip_gpio_set_debounce() local
206 div = (unsigned long)debounce * freq; in rockchip_gpio_set_debounce()
207 div_reg = DIV_ROUND_CLOSEST_ULL(div, 0x2 * USEC_PER_SEC) - 1; in rockchip_gpio_set_debounce()
/device/soc/rockchip/common/sdk_linux/drivers/gpio/
H A Dgpio-rockchip.c196 u64 div; in rockchip_gpio_set_debounce() local
209 div = debounce * freq; in rockchip_gpio_set_debounce()
210 div_reg = DIV_ROUND_CLOSEST_ULL(div, 0x2 * USEC_PER_SEC) - 1; in rockchip_gpio_set_debounce()
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/
H A Dsiutils.c1819 divide_clock(uint32 clock, uint32 div) in divide_clock() argument
1821 return div ? clock / div : 0; in divide_clock()
2107 uint div; in si_slowclk_freq() local
2121 div = 4 * in si_slowclk_freq()
2126 return (max_freq ? (XTALMAXFREQ / div) : (XTALMINFREQ / div)); in si_slowclk_freq()
2128 return (max_freq ? (PCIMAXFREQ / div) : (PCIMINFREQ / div)); in si_slowclk_freq()
2133 div in si_slowclk_freq()
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/device/soc/rockchip/rk3588/kernel/drivers/gpio/
H A Dgpio-rockchip.c197 u64 div; in rockchip_gpio_set_debounce() local
206 div = debounce * freq; in rockchip_gpio_set_debounce()
207 div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; in rockchip_gpio_set_debounce()
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-mipi-dsi.c41 #define TO_CLK_DIVISION(div) (((div)&0xff) << 8)
42 #define TX_ESC_CLK_DIVISION(div) ((div)&0xff)
/device/soc/rockchip/common/hardware/mpp/include/
H A Drk_venc_cmd.h429 signed int div; member
/device/soc/rockchip/rk3399/hardware/mpp/include/
H A Drk_venc_cmd.h430 RK_S32 div; member
/device/soc/rockchip/rk3568/hardware/mpp/include/
H A Drk_venc_cmd.h430 RK_S32 div; member
/device/soc/rockchip/rk3588/hardware/mpp/include/
H A Drk_venc_cmd.h509 RK_S32 div; member

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