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Searched refs:VADDR_T (Results 1 - 13 of 13) sorted by relevance

/device/qemu/drivers/virtio/
H A Dvirtrng.c70 q->desc[0].pAddr = VMM_TO_DMA_ADDR((VADDR_T)buffer); in VirtrngIO()
146 VADDR_T base; in VirtrngInitDev()
169 base = ALIGN((VADDR_T)rng + sizeof(struct Virtrng), VIRTQ_ALIGN_DESC); in VirtrngInitDev()
212 if (LOS_IsUserAddressRange((VADDR_T)buffer, bytes)) { in VirtrngRead()
218 } else if ((VADDR_T)buffer + bytes < (VADDR_T)buffer) { in VirtrngRead()
H A Dvirtmmio.c36 VADDR_T base; in VirtmmioDiscover()
163 static VADDR_T CalculateQueueAddr(VADDR_T base, uint16_t qsz, struct Virtq *q) in CalculateQueueAddr()
176 VADDR_T VirtmmioConfigQueue(struct VirtmmioDev *dev, VADDR_T base, uint16_t qsz[], int num) in VirtmmioConfigQueue()
H A Dvirtgpu.c210 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)req); in RequestResponse()
215 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)resp); in RequestResponse()
228 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)req); in RequestDataResponse()
233 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)data); in RequestDataResponse()
238 q->desc[idx].pAddr = VMM_TO_DMA_ADDR((VADDR_T)resp); in RequestDataResponse()
257 q->desc[head].pAddr = VMM_TO_DMA_ADDR((VADDR_T)req); in RequestNoResponse()
451 q->desc[i + 1].pAddr = VMM_TO_DMA_ADDR((VADDR_T)&g_virtGpu->resp); in PopulateVirtQ()
505 VADDR_T base; in VirtgpuInitDev()
527 base = ALIGN((VADDR_T)gpu + sizeof(struct Virtgpu), VIRTQ_ALIGN_DESC); in VirtgpuInitDev()
703 info->memphys = (void *)VMM_TO_DMA_ADDR((VADDR_T)g_virtGp in FbGetOverlayInfo()
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H A Dvirtmmio.h125 VADDR_T base; /* I/O base address */
147 VADDR_T VirtmmioConfigQueue(struct VirtmmioDev *dev, VADDR_T base, uint16_t qsz[], int len);
H A Dvirtblock.c128 q->desc[i].pAddr = VMM_TO_DMA_ADDR((VADDR_T)&blk->req); in PopulateRequestQ()
137 q->desc[i].pAddr = VMM_TO_DMA_ADDR((VADDR_T)&blk->resp); in PopulateRequestQ()
151 q->desc[1].pAddr = VMM_TO_DMA_ADDR((VADDR_T)buf); in VirtblkIO()
200 VADDR_T base; in VirtblkInitDev()
219 base = ALIGN((VADDR_T)blk + sizeof(struct Virtblk), VIRTQ_ALIGN_DESC); in VirtblkInitDev()
H A Dvirtinput.c116 q->desc[i].pAddr = VMM_TO_DMA_ADDR((VADDR_T)&in->ev[i]); in PopulateEventQ()
310 VADDR_T base; in VirtinInitDev()
331 base = ALIGN((VADDR_T)in + sizeof(struct Virtin), VIRTQ_ALIGN_DESC); in VirtinInitDev()
H A Dvirtnet.c181 paddr = VMM_TO_DMA_ADDR((VADDR_T)nic->rbuf[i]); in PopulateRxBuffer()
193 VADDR_T base; in ConfigQueue()
196 base = ALIGN((VADDR_T)nic + sizeof(struct VirtNetif), VIRTQ_ALIGN_DESC); in ConfigQueue()
/device/qemu/riscv32_virt/liteos_m/board/driver/
H A Dvirtmmio.h25 typedef unsigned long VADDR_T; typedef
136 VADDR_T base; /* I/O base address */
158 VADDR_T VirtmmioConfigQueue(struct VirtmmioDev *dev, VADDR_T base, uint16_t qsz[], int num);
H A Dvirtmmio.c41 VADDR_T base; in VirtmmioDiscover()
171 static VADDR_T CalculateQueueAddr(VADDR_T base, uint16_t qsz, struct Virtq *q) in CalculateQueueAddr()
184 VADDR_T VirtmmioConfigQueue(struct VirtmmioDev *dev, VADDR_T base, uint16_t qsz[], int num) in VirtmmioConfigQueue()
H A Dvirtgpu.c211 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)req)); in RequestResponse()
216 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)resp)); in RequestResponse()
229 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)req)); in RequestDataResponse()
234 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)data)); in RequestDataResponse()
239 q->desc[idx].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)resp)); in RequestDataResponse()
258 q->desc[head].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)req)); in RequestNoResponse()
454 q->desc[i + 1].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)&g_virtGpu->resp)); in PopulateVirtQ()
509 VADDR_T base; in VirtgpuInitDev()
535 base = ALIGN((VADDR_T)gpu + sizeof(struct Virtgpu), VIRTQ_ALIGN_DESC); in VirtgpuInitDev()
717 info->memphys = (void *)VMM_TO_DMA_ADDR((VADDR_T)g_virtGp in FbGetOverlayInfo()
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H A Dvirtnet.c243 static err_t ConfigRxBuffer(struct VirtNetif *nic, VADDR_T buf) in ConfigRxBuffer()
275 VADDR_T buf, pad; in ConfigQueue()
297 buf = VirtmmioConfigQueue(&nic->dev, (VADDR_T)base, qsz, VIRTQ_NUM_NET); in ConfigQueue()
398 VADDR_T payload; in LowLevelInput()
H A Dvirtinput.c118 q->desc[i].pAddr = u32_to_u64(VMM_TO_DMA_ADDR((VADDR_T)&in->ev[i])); in PopulateEventQ()
321 VADDR_T base; in VirtinInitDev()
344 base = ALIGN((VADDR_T)in + sizeof(struct Virtin), VIRTQ_ALIGN_DESC); in VirtinInitDev()
/device/qemu/drivers/char/mmz/
H A Dmmz.c65 VADDR_T vaddr; in MmzAlloc()
131 VADDR_T vaddr; in MmzMap()
183 return OsUnMMap(curVmSpace, (VADDR_T)mmzm->vaddr, mmzm->size); in MmzUnMap()
200 region = LOS_RegionFind(curVmSpace, (VADDR_T)(unsigned int)mmzm->vaddr); in MmzFree()

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