Home
last modified time | relevance | path

Searched refs:UD_REG_NAME (Results 1 - 5 of 5) sorted by relevance

/device/soc/hisilicon/common/platform/hieth-sf/src/
H A Deth_mac.c28 old = HiethReadlBits(ld, UD_REG_NAME(MAC_PORTSET), BITS_MACSTAT); in SetLinkStat()
29 HiethWritelBits(ld, mode, UD_REG_NAME(MAC_PORTSET), BITS_MACSTAT); in SetLinkStat()
37 old = HiethReadlBits(ld, UD_REG_NAME(MAC_PORTSEL), BITS_NEGMODE); in SetNegMode()
38 HiethWritelBits(ld, mode, UD_REG_NAME(MAC_PORTSEL), BITS_NEGMODE); in SetNegMode()
44 return HiethReadlBits(ld, UD_REG_NAME(MAC_PORTSEL), BITS_NEGMODE); in GetNegMode()
54 return HiethReadlBits(ld, UD_REG_NAME(MAC_RO_STAT), BITS_MACSTAT); in HiethGetLinkStat()
62 old = HiethReadlBits(ld, UD_REG_NAME(MAC_TX_IPGCTRL), BITS_PRE_CNT_LIMIT); in HiethSetMacLeadcodeCntLimit()
63 HiethWritelBits(ld, cnt, UD_REG_NAME(MAC_TX_IPGCTRL), BITS_PRE_CNT_LIMIT); in HiethSetMacLeadcodeCntLimit()
79 old = HiethReadlBits(ld, UD_REG_NAME(MAC_TX_IPGCTRL), BITS_IPG); in HiethSetMacTransIntervalBits()
80 HiethWritelBits(ld, nbits, UD_REG_NAME(MAC_TX_IPGCTR in HiethSetMacTransIntervalBits()
[all...]
H A Dctrl.c105 HiethWritelBits(ld, drop, UD_REG_NAME(GLB_RX_COE_CTRL), BITS_COE_IPHDR_DROP); in HiethEnableRxcsumDrop()
106 HiethWritelBits(ld, false, UD_REG_NAME(GLB_RX_COE_CTRL), BITS_COE_PAYLOAD_DROP); in HiethEnableRxcsumDrop()
107 HiethWritelBits(ld, drop, UD_REG_NAME(GLB_RX_COE_CTRL), BITS_COE_IPV6_UDP_ZERO_DROP); in HiethEnableRxcsumDrop()
223 return HiethReadlBits(ld, UD_REG_NAME(GLB_RO_QUEUE_STAT), BITS_XMITQ_RDY); in TestXmitQueueReady()
278 HiethWritelBits(ld, ld->depth.hwXmitq, UD_REG_NAME(GLB_QLEN_SET), BITS_TXQ_DEP); in HiethSetHwqDepth()
279 HiethWritelBits(ld, HIETH_MAX_QUEUE_DEPTH - ld->depth.hwXmitq, UD_REG_NAME(GLB_QLEN_SET), BITS_RXQ_DEP); in HiethSetHwqDepth()
384 while (HiethReadlBits(ld, UD_REG_NAME(GLB_RO_QUEUE_STAT), BITS_RECVQ_RDY)) { in HiethFeedHw()
411 HiethWrite(ld, VMM_TO_DMA_ADDR((UINTPTR)NetBufGetAddress(netBuf, E_DATA_BUF)), UD_REG_NAME(GLB_IQ_ADDR)); in HiethFeedHw()
/device/soc/hisilicon/common/platform/hieth-sf/include/internal/
H A Dctrl.h278 #define HwGetRxpkgInfo(ld) HiethRead(ld, UD_REG_NAME(GLB_RO_IQFRM_DES))
280 #define HwXmitqCntInUse(ld) HiethReadlBits(ld, UD_REG_NAME(GLB_RO_QUEUE_STAT), BITS_XMITQ_CNT_INUSE)
284 HiethWrite(ld, (addr), UD_REG_NAME(GLB_EQ_ADDR)); \
285 HiethWritelBits(ld, (len), UD_REG_NAME(GLB_EQFRM_LEN), BITS_TXINQ_LEN); \
H A Dhieth_pri.h186 #define UD_REG_NAME(name) ((ld->port == UP_PORT) ? U_##name : D_##name) macro
/device/soc/hisilicon/common/platform/hieth-sf/adapter/
H A Dhieth_mac.c91 HiethWritelBits(ld, 1, UD_REG_NAME(GLB_TSO_DBG_EN), BITS_TSO_DBG_EN); in HiethPortInit()

Completed in 3 milliseconds