Searched refs:UD_BIT_NAME (Results 1 - 4 of 4) sorted by relevance
| /device/soc/hisilicon/common/platform/hieth-sf/adapter/ |
| H A D | hieth_mac.c | 84 HiethClearIrqstatus(ld, UD_BIT_NAME(BITS_IRQS_MASK));
in HiethPortInit()
86 HiethWritelBits(ld, 0, GLB_RW_IRQ_ENA, UD_BIT_NAME(BITS_IRQS_ENA));
in HiethPortInit()
87 HiethIrqDisable(ld, UD_BIT_NAME(BITS_IRQS_MASK));
in HiethPortInit()
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| /device/soc/hisilicon/common/platform/hieth-sf/src/ |
| H A D | interface.c | 277 HiethClearIrqstatus(ld, UD_BIT_NAME(HIETH_INT_TXQUE_RDY)); in HiethDeliver()
281 if ((ints & UD_BIT_NAME(HIETH_INT_MULTI_RXRDY))) { in HiethDeliver()
542 HiethClearIrqstatus(ld, UD_BIT_NAME(BITS_IRQS_MASK)); in RegisterHiethData()
556 HiethIrqEnable(ld, UD_BIT_NAME(HIETH_INT_MULTI_RXRDY) | UD_BIT_NAME(HIETH_INT_TXQUE_RDY)); in RegisterHiethData()
557 HiethWritelBits(ld, 1, GLB_RW_IRQ_ENA, UD_BIT_NAME(BITS_IRQS_ENA)); in RegisterHiethData()
560 HiethIrqEnable(ld, UD_BIT_NAME(HIETH_INT_TX_ERR)); in RegisterHiethData()
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| /device/soc/hisilicon/common/platform/hieth-sf/include/internal/ |
| H A D | ctrl.h | 274 #define IsRecvPacket(ld) (HiethRead(ld, GLB_RW_IRQ_RAW) & (UD_BIT_NAME(HIETH_INT_RX_RDY)))
276 #define HwSetRxpkgFinish(ld) HiethWrite(ld, UD_BIT_NAME(HIETH_INT_RX_RDY), GLB_RW_IRQ_RAW)
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| H A D | hieth_pri.h | 187 #define UD_BIT_NAME(name) ((ld->port == UP_PORT) ? name##_U : name##_D) macro
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