Searched refs:UART_CR (Results 1 - 12 of 12) sorted by relevance
| /device/soc/hisilicon/common/platform/uart/ |
| H A D | uart_pl011.c | 183 cr = OSAL_READW(port->physBase + UART_CR); in Pl011ConfigIn()
187 OSAL_WRITEW(0, port->physBase + UART_CR); in Pl011ConfigIn()
203 OSAL_WRITEW(cr, port->physBase + UART_CR); in Pl011ConfigIn()
213 OSAL_WRITEW(cr, port->physBase + UART_CR); in Pl011ConfigIn()
237 OSAL_WRITEW(0, port->physBase + UART_CR); in Pl011StartUp()
255 cr = OSAL_READW(port->physBase + UART_CR); in Pl011StartUp()
257 OSAL_WRITEL(cr, port->physBase + UART_CR); in Pl011StartUp()
283 reg_tmp = OSAL_READW(port->physBase + UART_CR); in Pl011ShutDown()
287 OSAL_WRITEW(reg_tmp, port->physBase + UART_CR); in Pl011ShutDown()
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| H A D | uart_pl011.h | 40 #define UART_CR 0x30 /* control register */ macro
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| H A D | uart_hi35xx.c | 44 {"UART_CR", PLATFORM_DUMPER_REGISTERL, (void *)(port->physBase + UART_CR)}, in UartDumperDump()
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| /device/qemu/drivers/uart/ |
| H A D | uart_pl011.c | 184 cr = OSAL_READW(port->physBase + UART_CR); in Pl011ConfigIn()
188 OSAL_WRITEW(0, port->physBase + UART_CR); in Pl011ConfigIn()
204 OSAL_WRITEW(cr, port->physBase + UART_CR); in Pl011ConfigIn()
214 OSAL_WRITEW(cr, port->physBase + UART_CR); in Pl011ConfigIn()
238 OSAL_WRITEW(0, port->physBase + UART_CR); in Pl011StartUp()
256 cr = OSAL_READW(port->physBase + UART_CR); in Pl011StartUp()
258 OSAL_WRITEL(cr, port->physBase + UART_CR); in Pl011StartUp()
284 reg_tmp = OSAL_READW(port->physBase + UART_CR); in Pl011ShutDown()
288 OSAL_WRITEW(reg_tmp, port->physBase + UART_CR); in Pl011ShutDown()
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| H A D | uart_pl011.h | 40 #define UART_CR 0x30 /* control register */ macro
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/uart/ |
| H A D | hi_uart.c | 40 #define UART_CR 0x30 macro
453 g_uart_regs_save[port_num].cr = hi_reg_read_val16(udd->phys_base + UART_CR); in hi_uart_lp_save()
474 hi_reg_write16((phys_base + UART_CR), 0); in hi_uart_lp_restore()
488 temp = hi_reg_read_val16(phys_base + UART_CR); in hi_uart_lp_restore()
491 hi_reg_write16(phys_base + UART_CR, temp); /* 14 15 bit */ in hi_uart_lp_restore()
494 temp = hi_reg_read_val16(phys_base + UART_CR); in hi_uart_lp_restore()
496 hi_reg_write16((phys_base + UART_CR), temp); in hi_uart_lp_restore()
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| H A D | serial_dw.h | 80 #define UART_CR 0x30 macro
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| /device/qemu/arm_virt/liteos_a_mini/board/amba_pl011/ |
| H A D | amba_pl011.h | 47 #define UART_CR 0x30 /* control register */
macro
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| H A D | amba_pl011.c | 177 UARTREG(UART_REG_BASE, UART_CR) = (1 << 8) | (1 << 0);
in uart_early_init()
199 UARTREG(UART_REG_BASE, UART_CR) |= (1 << 9);
in uart_init()
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| /device/qemu/arm_virt/liteos_a/board/amba_pl011/ |
| H A D | amba_pl011.h | 47 #define UART_CR 0x30 /* control register */
macro
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| H A D | amba_pl011.c | 177 UARTREG(UART_REG_BASE, UART_CR) = (1 << 8) | (1 << 0);
in uart_early_init()
199 UARTREG(UART_REG_BASE, UART_CR) |= (1 << 9);
in uart_init()
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/boot/loaderboot/fixed/include/ |
| H A D | serial_dw.h | 29 #define UART_CR 0x30 macro
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