| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/ |
| H A D | mali_kbase_hw.c | 148 {U32_MAX /* sentinel value */, NULL}}}, in kbase_hw_get_issues_for_new_id()
157 {U32_MAX, NULL}}}, in kbase_hw_get_issues_for_new_id()
165 {U32_MAX, NULL}}}, in kbase_hw_get_issues_for_new_id()
167 {GPU_ID2_PRODUCT_TDVX, {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tDVx_r0p0}, {U32_MAX, NULL}}}, in kbase_hw_get_issues_for_new_id()
169 {GPU_ID2_PRODUCT_TNOX, {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tNOx_r0p0}, {U32_MAX, NULL}}}, in kbase_hw_get_issues_for_new_id()
174 {U32_MAX, NULL}}}, in kbase_hw_get_issues_for_new_id()
182 {U32_MAX, NULL}}}, in kbase_hw_get_issues_for_new_id()
191 {U32_MAX, NULL}}}, in kbase_hw_get_issues_for_new_id()
196 {U32_MAX, NULL}}}, in kbase_hw_get_issues_for_new_id()
203 {U32_MAX, NUL in kbase_hw_get_issues_for_new_id()
[all...] |
| H A D | mali_malisw.h | 38 #define U32_MAX ((u32)~0U) macro
39 #define S32_MAX ((s32)(U32_MAX >> 1))
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| H A D | mali_kbase_dummy_job_wa.c | 118 kbase_reg_write(kbdev, JOB_SLOT_REG(slot, JS_HEAD_NEXT_LO), jc & U32_MAX); in run_job()
120 kbase_reg_write(kbdev, JOB_SLOT_REG(slot, JS_AFFINITY_NEXT_LO), cores & U32_MAX); in run_job()
172 kbase_reg_write(kbdev, SHADER_PWRON_LO, (cores & U32_MAX)); in kbase_dummy_job_wa_execute()
177 wait(kbdev, SHADER_READY_LO, (cores & U32_MAX), true); in kbase_dummy_job_wa_execute()
210 kbase_reg_write(kbdev, SHADER_PWROFF_LO, (cores & U32_MAX)); in kbase_dummy_job_wa_execute()
214 wait(kbdev, SHADER_READY_LO, (cores & U32_MAX), false); in kbase_dummy_job_wa_execute()
215 wait(kbdev, SHADER_PWRTRANS_LO, (cores & U32_MAX), false); in kbase_dummy_job_wa_execute()
220 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), U32_MAX); in kbase_dummy_job_wa_execute()
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| H A D | mali_kbase_hwcnt_types.h | 968 accumulated = U32_MAX; in kbase_hwcnt_dump_buffer_block_accumulate()
1032 accumulated = U32_MAX; in kbase_hwcnt_dump_buffer_block_accumulate_strict()
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| H A D | mali_kbase_js_ctx_attr.c | 148 KBASE_DEBUG_ASSERT(js_kctx_info->ctx.ctx_attr_ref_count[attribute] < U32_MAX); in kbasep_js_ctx_attr_ctx_retain_attr()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/ |
| H A D | mali_kbase_hw.c | 144 { U32_MAX /* sentinel value */, NULL } } }, in kbase_hw_get_issues_for_new_id()
153 { U32_MAX, NULL } } }, in kbase_hw_get_issues_for_new_id()
161 { U32_MAX, NULL } } }, in kbase_hw_get_issues_for_new_id()
165 { U32_MAX, NULL } } }, in kbase_hw_get_issues_for_new_id()
169 { U32_MAX, NULL } } }, in kbase_hw_get_issues_for_new_id()
174 { U32_MAX, NULL } } }, in kbase_hw_get_issues_for_new_id()
182 { U32_MAX, NULL } } }, in kbase_hw_get_issues_for_new_id()
191 { U32_MAX, NULL } } }, in kbase_hw_get_issues_for_new_id()
196 { U32_MAX, NULL } } }, in kbase_hw_get_issues_for_new_id()
203 { U32_MAX, NUL in kbase_hw_get_issues_for_new_id()
[all...] |
| H A D | mali_kbase_dummy_job_wa.c | 120 jc & U32_MAX); in run_job()
124 cores & U32_MAX); in run_job()
181 kbase_reg_write(kbdev, SHADER_PWRON_LO, (cores & U32_MAX)); in kbase_dummy_job_wa_execute()
186 wait(kbdev, SHADER_READY_LO, (cores & U32_MAX), true); in kbase_dummy_job_wa_execute()
217 kbase_reg_write(kbdev, SHADER_PWROFF_LO, (cores & U32_MAX)); in kbase_dummy_job_wa_execute()
221 wait(kbdev, SHADER_READY_LO, (cores & U32_MAX), false); in kbase_dummy_job_wa_execute()
222 wait(kbdev, SHADER_PWRTRANS_LO, (cores & U32_MAX), false); in kbase_dummy_job_wa_execute()
227 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), U32_MAX); in kbase_dummy_job_wa_execute()
|
| H A D | mali_kbase_hwcnt_gpu_narrow.c | 248 (src_blk[val] > U32_MAX) ? U32_MAX : (u32)src_blk[val]; in kbase_hwcnt_dump_buffer_block_copy_strict_narrow()
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| H A D | mali_kbase_js_ctx_attr.c | 153 KBASE_DEBUG_ASSERT(js_kctx_info->ctx.ctx_attr_ref_count[attribute] < U32_MAX); in kbasep_js_ctx_attr_ctx_retain_attr()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/ |
| H A D | mali_kbase_hw.c | 130 {U32_MAX /* sentinel value */, NULL}}},
in kbase_hw_get_issues_for_new_id()
136 {U32_MAX, NULL}}},
in kbase_hw_get_issues_for_new_id()
145 {U32_MAX, NULL}}},
in kbase_hw_get_issues_for_new_id()
148 {GPU_ID2_PRODUCT_TKAX, {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tKAx_r0p0}, {U32_MAX, NULL}}},
in kbase_hw_get_issues_for_new_id()
152 {GPU_ID2_PRODUCT_TTRX, {{GPU_ID2_VERSION_MAKE(0, 0, 0), base_hw_issues_tTRx_r0p0}, {U32_MAX, NULL}}},
in kbase_hw_get_issues_for_new_id()
177 for (v = 0; product->map[v].version != U32_MAX; ++v) {
in kbase_hw_get_issues_for_new_id()
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| H A D | mali_malisw.h | 31 #define U32_MAX ((u32)~0U) macro
32 #define S32_MAX ((s32)(U32_MAX >> 1))
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| H A D | mali_kbase_js_ctx_attr.c | 141 KBASE_DEBUG_ASSERT(js_kctx_info->ctx.ctx_attr_ref_count[attribute] < U32_MAX); in kbasep_js_ctx_attr_ctx_retain_attr()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/ |
| H A D | mali_kbase_hw.c | 136 {U32_MAX /* sentinel value */, NULL} } }, in kbase_hw_get_issues_for_new_id()
142 {U32_MAX, NULL} } }, in kbase_hw_get_issues_for_new_id()
151 {U32_MAX, NULL} } }, in kbase_hw_get_issues_for_new_id()
157 {U32_MAX, NULL} } }, in kbase_hw_get_issues_for_new_id()
163 {U32_MAX, NULL} } }, in kbase_hw_get_issues_for_new_id()
188 for (v = 0; product->map[v].version != U32_MAX; ++v) { in kbase_hw_get_issues_for_new_id()
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| H A D | mali_malisw.h | 33 #define U32_MAX ((u32)~0U) macro
34 #define S32_MAX ((s32)(U32_MAX>>1))
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| H A D | mali_kbase_js_ctx_attr.c | 141 KBASE_DEBUG_ASSERT(js_kctx_info->ctx.ctx_attr_ref_count[attribute] < U32_MAX); in kbasep_js_ctx_attr_ctx_retain_attr()
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| /device/soc/hisilicon/hi3751v350/sdk_linux/source/common/include/ |
| H A D | hi_type.h | 52 #ifndef U32_MAX
53 #define U32_MAX (~0U) macro
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/ipa_control/ |
| H A D | mali_kbase_csf_ipa_control.c | 116 u32 select_cshw_lo = (u32)(select[KBASE_IPA_CORE_TYPE_CSHW] & U32_MAX); in apply_select_config()
118 (u32)((select[KBASE_IPA_CORE_TYPE_CSHW] >> 32) & U32_MAX); in apply_select_config()
120 (u32)(select[KBASE_IPA_CORE_TYPE_MEMSYS] & U32_MAX); in apply_select_config()
122 (u32)((select[KBASE_IPA_CORE_TYPE_MEMSYS] >> 32) & U32_MAX); in apply_select_config()
124 (u32)(select[KBASE_IPA_CORE_TYPE_TILER] & U32_MAX); in apply_select_config()
126 (u32)((select[KBASE_IPA_CORE_TYPE_TILER] >> 32) & U32_MAX); in apply_select_config()
128 (u32)(select[KBASE_IPA_CORE_TYPE_SHADER] & U32_MAX); in apply_select_config()
130 (u32)((select[KBASE_IPA_CORE_TYPE_SHADER] >> 32) & U32_MAX); in apply_select_config()
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| /device/soc/rockchip/rk3588/kernel/drivers/mmc/host/ |
| H A D | cqhci-crypto.h | 29 WARN_ON_ONCE(mrq->crypto_ctx->bc_dun[0] > U32_MAX); in cqhci_crypto_prep_task_desc()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/ipa/backend/ |
| H A D | mali_kbase_ipa_counter_common_jm.c | 49 return (val > U32_MAX) ? U32_MAX : (u32)val; in kbase_ipa_read_hwcnt()
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| H A D | mali_kbase_ipa_counter_common_csf.c | 307 if (*cnt_values_p > U32_MAX) { in kbase_ipa_counter_dynamic_coeff()
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| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/thirdparty/ |
| H A D | mali_kbase_mmap.c | 79 unsigned long mask = ~((unsigned long)U32_MAX); in align_and_check()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/thirdparty/ |
| H A D | mali_kbase_mmap.c | 61 unsigned long mask = ~((unsigned long)U32_MAX); in align_and_check()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/ |
| H A D | mali_kbase_csf_scheduler.c | 36 #define KBASEP_GROUP_PREPARED_SEQ_NUM_INVALID (U32_MAX)
626 if (!WARN_ON(prev_count == U32_MAX)) in scheduler_pm_active_handle_suspend()
675 if (!WARN_ON(prev_count == U32_MAX)) in scheduler_pm_active_after_sleep()
1323 queue->trace_buffer_base & U32_MAX); in program_cs_trace_cfg()
1329 queue->trace_offset_ptr & U32_MAX); in program_cs_trace_cfg()
2391 compute_mask & U32_MAX); in program_csg_slot()
2395 fragment_mask & U32_MAX); in program_csg_slot()
2399 tiler_mask & U32_MAX); in program_csg_slot()
2415 normal_suspend_buf & U32_MAX); in program_csg_slot()
2424 protm_suspend_buf & U32_MAX); in program_csg_slot()
[all...] |
| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/ |
| H A D | mali_kbase_model_dummy.c | 518 return (value & U32_MAX); in gpu_model_get_prfcnt_value()
1244 ipa_ctl_select_config[core_type] &= ~(u64)U32_MAX;
1247 ipa_ctl_select_config[core_type] &= U32_MAX;
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| /device/soc/rockchip/common/sdk_linux/include/linux/ |
| H A D | dma-mapping.h | 473 * If @dev is NULL a boundary of U32_MAX is assumed, this case is just for
479 return (U32_MAX >> page_shift) + 1; in dma_get_seg_boundary_nr_pages()
|