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Searched refs:SYS_CTRL_REG_BASE (Results 1 - 21 of 21) sorted by relevance

/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/include/
H A Dplatform.h40 #define SYS_CTRL_REG_BASE 0x12020000 macro
41 #define REG_BASE_SCTL SYS_CTRL_REG_BASE
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/include/
H A Dplatform.h40 #define SYS_CTRL_REG_BASE 0x12020000 macro
41 #define REG_BASE_SCTL SYS_CTRL_REG_BASE
/device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/
H A Dnand.h45 #define check_boot_type() ((readl(SYS_CTRL_REG_BASE + REG_SYSSTAT) >> 4) & 0x3);
H A Dsys_ctrl.h42 #define REG_START_FLAG (SYS_CTRL_REG_BASE + REG_SC_GEN1)
H A Dspinor.h45 start_up_mode = readl(IO_ADDRESS(SYS_CTRL_REG_BASE + SFC_ADDR_MODE_REG)); \
H A Dflash.h57 regval = readl(SYS_CTRL_REG_BASE + REG_SYSSTAT); \
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/hisoc/
H A Dsys_ctrl.h42 #define REG_START_FLAG (SYS_CTRL_REG_BASE + REG_SC_GEN1)
H A Dnand.h45 #define check_boot_type() ((readl(SYS_CTRL_REG_BASE + REG_SYSSTAT) >> 4) & 0x3);
H A Dspinor.h45 start_up_mode = readl(IO_ADDRESS(SYS_CTRL_REG_BASE + SFC_ADDR_MODE_REG)); \
H A Dflash.h57 regval = readl(SYS_CTRL_REG_BASE + REG_SYSSTAT); \
/device/qemu/arm_virt/liteos_a/board/include/soc/
H A Dsys_ctrl.h42 #define REG_START_FLAG (SYS_CTRL_REG_BASE + REG_SC_GEN1)
/device/qemu/arm_virt/liteos_a/board/
H A Dplatform.c47 writel(0xffffffff, (SYS_CTRL_REG_BASE + REG_SC_SYSRES)); in OsReboot()
H A Dtarget_config.h28 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) macro
/device/qemu/arm_virt/liteos_a_mini/board/
H A Dtarget_config.h28 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) macro
/device/board/hisilicon/hispark_aries/liteos_a/board/
H A Dtarget_config.h27 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) macro
/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/
H A Dstart.S107 ldr r0, =SYS_CTRL_REG_BASE
128 ldr r0, =SYS_CTRL_REG_BASE
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/boot/
H A Dstart.S107 ldr r0, =SYS_CTRL_REG_BASE
128 ldr r0, =SYS_CTRL_REG_BASE
/device/board/hisilicon/hispark_taurus/liteos_a/board/
H A Dtarget_config.h27 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) macro
/device/board/hisilicon/hispark_aries/liteos_a/board/include/asm/
H A Dplatform.h99 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) macro
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/asm/
H A Dplatform.h95 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) macro
/device/soc/hisilicon/common/platform/hieth-sf/src/
H A Dctrl.c62 val = readl(SYS_CTRL_REG_BASE + 0x8024); in HiethFephyTrim()

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