SCLK_UART0_PMU (reference) in projects: device

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/device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/
H A D	rk1808-cru.h	`105 #define SCLK_UART0_PMU 104 macro`
H A D	px30-cru.h	`188 #define SCLK_UART0_PMU 6 macro`
/device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/
H A D	rk1808-cru.h	`105 #define SCLK_UART0_PMU 104 macro`
/device/soc/rockchip/common/vendor/drivers/clk/
H A D	clk-rk1808.c	`784 GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT, RK1808_PMU_CLKGATE_CON(1), 3,`
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A D	clk-px30.c	`707 GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT, PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),`