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Searched refs:SCLK_PWM0 (Results 1 - 6 of 6) sorted by relevance

/device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/
H A Drk1808-cru.h85 #define SCLK_PWM0 84 macro
H A Dpx30-cru.h36 #define SCLK_PWM0 34 macro
/device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/
H A Drk1808-cru.h85 #define SCLK_PWM0 84 macro
/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-rk1808.c687 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0, RK1808_CLKSEL_CON(69), 7, 1, MFLAGS, 0, 7, DFLAGS,
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-rk3308.c317 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0, RK3308_CLKSEL_CON(29), 14, 2, MFLAGS, 0, 7, DFLAGS,
H A Dclk-px30.c522 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0, PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS,

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