Searched refs:SCLK_EMMC_DIV50 (Results 1 - 6 of 6) sorted by relevance
| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 42 #define SCLK_EMMC_DIV50 41 macro
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| H A D | px30-cru.h | 85 #define SCLK_EMMC_DIV50 83 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 42 #define SCLK_EMMC_DIV50 41 macro
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 478 COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_24m_p, CLK_IGNORE_UNUSED,
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3308.c | 399 COMPOSITE(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
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| H A D | clk-px30.c | 362 COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_xin24m_p, 0, PX30_CLKSEL_CON(20), 14, 2,
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