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Searched refs:PMU_CMU_CTL_BASE (Results 1 - 3 of 3) sorted by relevance

/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi3861_platform_base.h244 #define PMU_CMU_CTL_BASE 0x50002000 macro
245 #define PMU_CMU_CTL_GP_REG0_REG (PMU_CMU_CTL_BASE + 0x010)
246 #define PMU_CMU_CTL_GP_REG1_REG (PMU_CMU_CTL_BASE + 0x014)
247 #define PMU_CMU_CTL_GP_REG2_REG (PMU_CMU_CTL_BASE + 0x018)
248 #define PMU_CMU_CTL_GP_REG3_REG (PMU_CMU_CTL_BASE + 0x01C)
249 #define PMU_CMU_CTL_UDSLEEP_BUTTON_CTRL_REG (PMU_CMU_CTL_BASE + 0x020)
250 #define PMU_CMU_CTL_UDSLEEP_BUTTON_RPT_REG (PMU_CMU_CTL_BASE + 0x024)
251 #define PMU_CMU_CTL_UDSLEEP_BUTTON_INT_EN_REG (PMU_CMU_CTL_BASE + 0x028)
252 #define PMU_CMU_CTL_FUSE_L_REG (PMU_CMU_CTL_BASE + 0x040)
253 #define PMU_CMU_CTL_FUSE_H_REG (PMU_CMU_CTL_BASE
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/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/commonboot/
H A Dhi3861_platform.h99 #define PMU_CMU_CTL_BASE 0x50002000 macro
100 #define PMU_CMU_CTL_UDSLEEP_BUTTON_CTRL_REG (PMU_CMU_CTL_BASE + 0x020)
101 #define PMU_CMU_CTL_UDSLEEP_BUTTON_RPT_REG (PMU_CMU_CTL_BASE + 0x024)
102 #define PMU_CMU_CTL_OSC_TRIM_REG (PMU_CMU_CTL_BASE + 0x028)
103 #define PMU_CMU_CTL_PMU_MAN_CLR_0_REG (PMU_CMU_CTL_BASE + 0x104)
104 #define PMU_CMU_CTL_FLASHLDO_CFG_1_REG (PMU_CMU_CTL_BASE + 0x260)
105 #define PMU_CMU_CTL_GATE_TSENSOR_VDDIO_REG (PMU_CMU_CTL_BASE + 0x350)
106 #define PMU_CMU_CTL_CMU_DBG_SEL_REG (PMU_CMU_CTL_BASE + 0x414)
107 #define PMU_CMU_CTL_CLK_480M_GT_REG (PMU_CMU_CTL_BASE + 0x420)
108 #define PMU_CMU_CTL_CLK_192M_GT_REG (PMU_CMU_CTL_BASE
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H A Dboot_rom.h28 #define PMU_CMU_CTL_GP_REG0_REG (PMU_CMU_CTL_BASE + 0x010)
29 #define PMU_CMU_CTL_GP_REG1_REG (PMU_CMU_CTL_BASE + 0x014)
30 #define PMU_CMU_CTL_GP_REG2_REG (PMU_CMU_CTL_BASE + 0x018)
31 #define PMU_CMU_CTL_GP_REG3_REG (PMU_CMU_CTL_BASE + 0x01C)

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