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Searched refs:MIDGARD_MMU_BOTTOMLEVEL (Results 1 - 15 of 15) sorted by relevance

/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/mmu/
H A Dmali_kbase_mmu_mode_aarch64.c113 if (level == MIDGARD_MMU_BOTTOMLEVEL) { in ate_is_valid()
123 if (level == MIDGARD_MMU_BOTTOMLEVEL) { in pte_is_valid()
164 if (level == MIDGARD_MMU_BOTTOMLEVEL) { in entry_set_ate()
H A Dmali_kbase_mmu.c1027 return mmu_get_pgd_at_level(kbdev, mmut, vpfn, MIDGARD_MMU_BOTTOMLEVEL, out_pgd); in mmu_get_bottom_pgd()
1061 for (level = MIDGARD_MMU_TOPLEVEL; level <= MIDGARD_MMU_BOTTOMLEVEL; level++) { in mmu_insert_pages_failure_recovery()
1076 case MIDGARD_MMU_BOTTOMLEVEL: in mmu_insert_pages_failure_recovery()
1158 err = kbase_mem_pool_grow(&kbdev->mem_pools.small[kctx->mmu.group_id], MIDGARD_MMU_BOTTOMLEVEL); in kbase_mmu_insert_single_page()
1192 pgd_page[ofs] = kbase_mmu_create_ate(kbdev, phys, flags, MIDGARD_MMU_BOTTOMLEVEL, group_id); in kbase_mmu_insert_single_page()
1285 cur_level = MIDGARD_MMU_BOTTOMLEVEL; in kbase_mmu_insert_pages_no_flush()
1600 for (level = MIDGARD_MMU_TOPLEVEL; level <= MIDGARD_MMU_BOTTOMLEVEL; level++) { in kbase_mmu_teardown_pages()
1651 case MIDGARD_MMU_BOTTOMLEVEL: in kbase_mmu_teardown_pages()
1749 err = kbase_mem_pool_grow(&kbdev->mem_pools.small[kctx->mmu.group_id], MIDGARD_MMU_BOTTOMLEVEL); in kbase_mmu_update_pages_no_flush()
1766 pgd_page[index + i] = kbase_mmu_create_ate(kbdev, phys[i], flags, MIDGARD_MMU_BOTTOMLEVEL, group_i in kbase_mmu_update_pages_no_flush()
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/mmu/
H A Dmali_kbase_mmu_mode_aarch64.c97 if (level == MIDGARD_MMU_BOTTOMLEVEL) in ate_is_valid()
106 if (level == MIDGARD_MMU_BOTTOMLEVEL) in pte_is_valid()
148 if (level == MIDGARD_MMU_BOTTOMLEVEL) in entry_set_ate()
H A Dmali_kbase_mmu.c1270 return mmu_get_pgd_at_level(kbdev, mmut, vpfn, MIDGARD_MMU_BOTTOMLEVEL, in mmu_get_bottom_pgd()
1299 phys_addr_t pgds[MIDGARD_MMU_BOTTOMLEVEL + 1]; in mmu_insert_pages_failure_recovery()
1308 level <= MIDGARD_MMU_BOTTOMLEVEL; level++) { in mmu_insert_pages_failure_recovery()
1323 case MIDGARD_MMU_BOTTOMLEVEL: in mmu_insert_pages_failure_recovery()
1428 MIDGARD_MMU_BOTTOMLEVEL); in kbase_mmu_insert_single_page()
1473 phys, flags, MIDGARD_MMU_BOTTOMLEVEL, group_id); in kbase_mmu_insert_single_page()
1581 cur_level = MIDGARD_MMU_BOTTOMLEVEL; in kbase_mmu_insert_pages_no_flush()
2031 phys_addr_t pgds[MIDGARD_MMU_BOTTOMLEVEL + 1]; in kbase_mmu_teardown_pages()
2041 level <= MIDGARD_MMU_BOTTOMLEVEL; level++) { in kbase_mmu_teardown_pages()
2093 case MIDGARD_MMU_BOTTOMLEVEL in kbase_mmu_teardown_pages()
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/
H A Dmali_kbase_mmu.c464 for (l = MIDGARD_MMU_TOPLEVEL; l < MIDGARD_MMU_BOTTOMLEVEL; l++) { in mmu_get_bottom_pgd()
517 for (l = MIDGARD_MMU_TOPLEVEL; l < MIDGARD_MMU_BOTTOMLEVEL; l++) { in mmu_insert_pages_recover_get_bottom_pgd()
627 err = kbase_mem_pool_grow(&kctx->mem_pool, MIDGARD_MMU_BOTTOMLEVEL); in kbase_mmu_insert_single_page()
733 err = kbase_mem_pool_grow(&kctx->mem_pool, MIDGARD_MMU_BOTTOMLEVEL); in kbase_mmu_insert_pages_no_flush()
1116 err = kbase_mem_pool_grow(&kctx->mem_pool, MIDGARD_MMU_BOTTOMLEVEL); in kbase_mmu_update_pages()
1199 if (level < (MIDGARD_MMU_BOTTOMLEVEL - 1)) { in mmu_teardown_level()
1307 if (level < MIDGARD_MMU_BOTTOMLEVEL) { in kbasep_mmu_dump_level()
H A Dmali_kbase_context.c116 err = kbase_mem_pool_grow(&kctx->mem_pool, MIDGARD_MMU_BOTTOMLEVEL); in kbase_create_context()
H A Dmali_kbase_defs.h147 #define MIDGARD_MMU_BOTTOMLEVEL 3 macro
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/
H A Dmali_kbase_mmu.c502 for (l = MIDGARD_MMU_TOPLEVEL; l < MIDGARD_MMU_BOTTOMLEVEL; l++) { in mmu_get_bottom_pgd()
554 for (l = MIDGARD_MMU_TOPLEVEL; l < MIDGARD_MMU_BOTTOMLEVEL; l++) { in mmu_insert_pages_recover_get_bottom_pgd()
663 MIDGARD_MMU_BOTTOMLEVEL); in kbase_mmu_insert_single_page()
775 MIDGARD_MMU_BOTTOMLEVEL); in kbase_mmu_insert_pages_no_flush()
1166 MIDGARD_MMU_BOTTOMLEVEL); in kbase_mmu_update_pages()
1251 if (level < (MIDGARD_MMU_BOTTOMLEVEL - 1)) { in mmu_teardown_level()
1359 if (level < MIDGARD_MMU_BOTTOMLEVEL) { in kbasep_mmu_dump_level()
H A Dmali_kbase_context.c116 MIDGARD_MMU_BOTTOMLEVEL); in kbase_create_context()
H A Dmali_kbase_defs.h152 #define MIDGARD_MMU_BOTTOMLEVEL 3 macro
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/
H A Dmali_kbase_defs.h106 #define MIDGARD_MMU_BOTTOMLEVEL MIDGARD_MMU_LEVEL(3) macro
H A Dmali_kbase_softjobs.c1197 entry_mmu_flags = kbase_mmu_create_ate(kbdev, (struct tagged_addr) {0}, reg->flags, MIDGARD_MMU_BOTTOMLEVEL, in kbase_jit_allocate_process()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/
H A Dmali_kbase_defs.h101 #define MIDGARD_MMU_BOTTOMLEVEL MIDGARD_MMU_LEVEL(3) macro
H A Dmali_kbase_softjobs.c1230 MIDGARD_MMU_BOTTOMLEVEL, kctx->jit_group_id); in kbase_jit_allocate_process()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/
H A Dmali_kbase_csf_kcpu.c1511 MIDGARD_MMU_BOTTOMLEVEL, in KBASE_TLSTREAM_TL_KBASE_KCPUQUEUE_EXECUTE_JIT_ALLOC_INFO()

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