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Searched refs:IO_CTRL_REG_BASE_ADDR (Results 1 - 5 of 5) sorted by relevance

/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/io/
H A Dhi_flashboot_io.c24 #define IO_CTRL_REG_BASE_ADDR 0x904 /* Base address of the I/O control register, which is used to macro
53 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shift 2 bits */ in hi_io_get_pull()
70 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shift 2 bits */ in hi_io_set_driver_strength()
73 hi_reg_write((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shift 2 bits */ in hi_io_set_driver_strength()
85 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shift 2 bits */ in hi_io_get_driver_strength()
97 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << OFFSET_2_B)), reg_val); in hi_io_set_input_enable()
100 hi_reg_write((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << OFFSET_2_B)), reg_val); in hi_io_set_input_enable()
110 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << OFFSET_2_B)), reg_val); in hi_io_get_input_enable()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/startup/
H A Dmain.c75 hi_reg_read(HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR, reg_val); in boot_extern_32k()
82 hi_reg_write(HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR, reg_val); in boot_extern_32k()
H A Dmain.h23 #define IO_CTRL_REG_BASE_ADDR 0x904 /* Base address of the I/O control register, which is used to macro
/device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/src/
H A Dapp_main.c110 #ifndef IO_CTRL_REG_BASE_ADDR
111 #define IO_CTRL_REG_BASE_ADDR 0x904 macro
113 #define iocfg_reg_addr(_x) (HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + (_x) * 4)
/device/soc/hisilicon/hi3861v100/sdk_liteos/app/wifiiot_app/src/
H A Dapp_main.c95 #ifndef IO_CTRL_REG_BASE_ADDR
96 #define IO_CTRL_REG_BASE_ADDR 0x904 macro
98 #define iocfg_reg_addr(_x) (HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + (_x) * 4)

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